Abstract: An example design structure tangibly embodied in a machine readable medium includes a first arithmetic logic unit (ALU) to perform fixed point instructions using at least two general registers to read data from a first and second general register of a plurality of general registers and write a result in at least a third general register of the plurality of general registers. The design structure includes a second ALU to perform non-updating fixed point instructions using at least two general registers to only read data from the general registers. The design structure includes an efficiency logic unit coupled to the first ALU and the second ALU. The efficiency logic unit is to receive an instruction and determine whether the received instruction is an updating fixed point instruction or a non-updating fixed point instruction based on a number of general registers to be used to execute the received instruction.

Abstract: An example design structure tangibly embodied in a machine readable medium includes a first arithmetic logic unit (ALU) to perform fixed point instructions using at least two general registers to read data from a first and second general register of a plurality of general registers and write a result in at least a third general register of the plurality of general registers. The design structure includes a second ALU to perform non-updating fixed point instructions using at least two general registers to only read data from the general registers. The design structure includes an efficiency logic unit coupled to the first ALU and the second ALU. The efficiency logic unit is to receive an instruction and determine whether the received instruction is an updating fixed point instruction or a non-updating fixed point instruction based on a number of general registers to be used to execute the received instruction.

Abstract: Examples of techniques for designing processors are described herein. In one example, a design structure can be tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure can include a logic to determine whether a received instruction is an updating fixed point instruction or a non-updating fixed point instruction. The design structure can include a first arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be an updating fixed point instruction and store an update value in a general register. The design structure can include a second arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be a non-updating fixed point instruction.

Abstract: A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises generating a functional representation of logic to determine whether an instruction is an updating instruction or a non-updating instruction. The method further comprises generating a functional representation of a first arithmetic logic unit (ALU) coupled to a general register in the processor, the first ALU to execute the instruction if the instruction is an updating instruction and store an update value in the general register, and generating a functional representation of a second ALU in the processor to execute the instruction if the instruction is a non-updating instruction.

Abstract: Embodiments include issuing dynamic issue masks for processor hang prevention. Aspects include storing an instruction in an issue queue for execution by an execution unit, the instruction including a default issue mask. Aspects further include determining whether the instruction in the issue queue is likely to be rescinded by the execution unit. Based on determining that the instruction is not likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with the default issue mask. Based on determining that the instruction is likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with a likely to be rescinded issue mask.

Abstract: Embodiments include issuing dynamic issue masks for processor hang prevention. Aspects include storing an instruction in an issue queue for execution by an execution unit, the instruction including a default issue mask. Aspects further include determining whether the instruction in the issue queue is likely to be rescinded by the execution unit. Based on determining that the instruction is not likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with the default issue mask. Based on determining that the instruction is likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with a likely to be rescinded issue mask.

Abstract: A method and apparatus for tracing instruction streams for a multi-threaded processor are disclosed herein. In one embodiment, the apparatus includes a last thread register configured to store a thread index that indicates a last executed thread, a tracing memory configured to store, within each of a plurality of storage locations, state information corresponding to a dispatch cycle for a multi-threaded processor, and a tracing control module configured to provide the state information to the tracing memory. The state information includes instruction information and a previous thread index. The state information may also include a flip bit that is used to determine a current insertion point within the tracing memory. A corresponding method is also disclosed herein.

Abstract: An apparatus for processing instructions includes a mapping unit comprising a plurality of mappers wherein each mapper of the plurality of mappers maps a logical sub-register reference to a physical sub-register reference, a decoding unit configured to receive an instruction and determine a plurality of logical sub-register references therefrom, and an execution unit. The mapping unit may be configured to distribute the plurality of logical sub-register references amongst the plurality of mappers according to at least one bit in the instruction and provide a corresponding plurality of physical sub-register references. The execution unit may be configured to execute the instruction using the plurality of physical sub-register references. Corresponding methods are also disclosed herein.

Abstract: A method and apparatus for tracing instruction streams for a multi-threaded processor are disclosed herein. In one embodiment, the apparatus includes a last thread register configured to store a thread index that indicates a last executed thread, a tracing memory configured to store, within each of a plurality of storage locations, state information corresponding to a dispatch cycle for a multi-threaded processor, and a tracing control module configured to provide the state information to the tracing memory. The state information includes instruction information and a previous thread index. The state information may also include a flip bit that is used to determine a current insertion point within the tracing memory.

Abstract: An apparatus for processing instructions includes a mapping unit comprising a plurality of mappers wherein each mapper of the plurality of mappers maps a logical sub-register reference to a physical sub-register reference, a decoding unit configured to receive an instruction and determine a plurality of logical sub-register references therefrom, and an execution unit. The mapping unit may be configured to distribute the plurality of logical sub-register references amongst the plurality of mappers according to at least one bit in the instruction and provide a corresponding plurality of physical sub-register references. The execution unit may be configured to execute the instruction using the plurality of physical sub-register references. Corresponding methods are also disclosed herein.

Abstract: A method and apparatus for tracing instruction streams for a multi-threaded processor are disclosed herein. In one embodiment, the apparatus includes a last thread register configured to store a thread index that indicates a last executed thread, a tracing memory configured to store, within each of a plurality of storage locations, state information corresponding to a dispatch cycle for a multi-threaded processor, and a tracing control module configured to provide the state information to the tracing memory. The state information includes instruction information and a previous thread index. The state information may also include a flip bit that is used to determine a current insertion point within the tracing memory. A corresponding method is also disclosed herein.

Abstract: A method and apparatus for tracing instruction streams for a multi-threaded processor are disclosed herein. In one embodiment, the apparatus includes a last thread register configured to store a thread index that indicates a last executed thread, a tracing memory configured to store, within each of a plurality of storage locations, state information corresponding to a dispatch cycle for a multi-threaded processor, and a tracing control module configured to provide the state information to the tracing memory. The state information includes instruction information and a previous thread index. The state information may also include a flip bit that is used to determine a current insertion point within the tracing memory. A corresponding method is also disclosed herein.

Abstract: A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises generating a functional representation of logic to determine whether an instruction is an updating instruction or a non-updating instruction. The method further comprises generating a functional representation of a first arithmetic logic unit (ALU) coupled to a general register in the processor, the first ALU to execute the instruction if the instruction is an updating instruction and store an update value in the general register, and generating a functional representation of a second ALU in the processor to execute the instruction if the instruction is a non-updating instruction.

Abstract: Examples of techniques for designing processors are described herein. In one example, a design structure can be tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure can include a logic to determine whether a received instruction is an updating fixed point instruction or a non-updating fixed point instruction. The design structure can include a first arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be an updating fixed point instruction and store an update value in a general register. The design structure can include a second arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be a non-updating fixed point instruction.

Abstract: Embodiments include issuing dynamic issue masks for processor hang prevention. Aspects include storing an instruction in an issue queue for execution by an execution unit, the instruction including a default issue mask. Aspects further include determining whether the instruction in the issue queue is likely to be rescinded by the execution unit. Based on determining that the instruction is not likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with the default issue mask. Based on determining that the instruction is likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with a likely to be rescinded issue mask.

Abstract: Embodiments include issuing dynamic issue masks for processor hang prevention. Aspects include storing an instruction in an issue queue for execution by an execution unit, the instruction including a default issue mask. Aspects further include determining whether the instruction in the issue queue is likely to be rescinded by the execution unit. Based on determining that the instruction is not likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with the default issue mask. Based on determining that the instruction is likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with a likely to be rescinded issue mask.

Abstract: In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

Abstract: In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

Abstract: In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

Abstract: In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.