Abstract: A tool and method that automatically formats an Engineering Change Order (ECO), in a programming language suitable for processing by an Electronic Design Automation (EDA) tool, in order to specify metal-only design changes to complex hardware data-paths through changes in the netlist. The invention comprises an initial import component that imports a working netlist which serves as the baseline on which the tool operates. The tool further comprises four components: a bus extraction component, an index creation component, a text editor, and an ECO generation component. One or more buses are extracted from the working netlist and tabulated into an index table. The user uses a test editor to modify the index table to create a modified index table that embodies the desired design change. Finally, the ECO generation component automatically reconfigures the modified index table into an ECO format in a language usable by automated physical design tools.

Abstract: The present invention concerns a motion analysis system for analyzing the motion of an individual. The system has a control surface having one or more control areas, each control area corresponding to a predetermined instruction. An object is then held by an individual for use with the control surface. The system has a sensor for detecting the position of the object and producing a signal representative of the position. An analyzer then receives the signal from the sensor, wherein when the object is positioned at one of the control areas on the control surface the analyzer performs the predetermined instruction corresponding to the control area that the object is positioned.

Abstract: A memory apparatus includes a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller for regulating access to that buffer. Also included is a circuit, connected to each buffer controller and the receiving circuit, for accessing one or more of said buffers in response to a first serially stored instruction while, in response to at least one other serially stored instruction, concurrently accessing at least one remaining buffer.

Abstract: A graphics processor including an interface for providing triangle primitives representing a graphics image, a triangle interpolator coupled to the interface for interpolating a triangle primitive and serially computing multiple line primitives from the triangle primitive, a line renderer coupled to the triangle interpolator for receiving a line primitive from the triangle interpolator and for providing pixels representing the line primitive while the triangle interpolator is computing another line primitive.

Abstract: A graphics processor including an interface for providing triangle primitives and line primitives representing a graphical image, a line drawer for receiving line primitives and for rendering the line primitives, and a triangle interpolator for receiving the triangle primitives from the interface and for providing line primitives therefrom to the line drawer, wherein the interface includes a register for storing graphics image line primitives and for selectively providing the stored line primitives to the line drawer.

Abstract: A bitblt and line draw parameter calculator for preprocessing address information for a bitblt and line draw sequencer. The sequencer computes individual pixel addresses, controls color interpolation pacing and communicates with the memory hypervisor. By partitioning memory addressing into two tasks a first line or bitblt need only be partially processed prior to starting processing on a second line or bitblt.

Abstract: A data processing system is provided that includes a plurality of processors each including a circuit for providing a busy signal. The system also includes a plurality of registers for storing data wherein each register is dedicated to a selected processor or a selected set of processors. A control circuit is provided for receiving the busy signals and prohibiting storage from an external device to the registers dedicated a processor when that processor provides a busy signal.

Abstract: A modified dovetail joint interconnects a plywood web to a chord. The chord carries two grooves extending inwardly from the surface of the chord intersected by the web. The two grooves merge into a single, wider groove adjacent the surface of the chord, are separated by a wedge-shaped spacer, and are inclined relative to each other. The plywood web carries two flexible tongues along its edge portion that are sized to engage respective ones of the grooves in the chord. The tongues are composed, at least in part, of two of the veneer layers of the plywood and are spaced from each other by a web groove formed in an intervening layer of veneer. The inner terminus of the web groove as well as the terminus of the glue laminate between the tongue forming layers of veneer and the adjacent intervening layer both lie below the surface of the chord when the web and the chord are assembled.