Patents by Inventor Lee Fee Ngion

Lee Fee Ngion has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10654709
    Abstract: A shielded semiconductor device is assembled using a lead frame having a die receiving area, leads disposed around the die receiving area, and a bendable strip formed in the die receiving area. Each lead has an inner lead end that is spaced from but near to one of the sides of the die receiving area and an outer lead end that is distal to that side of the die receiving area. An IC die is attached to the die receiving area and electrically connected to the inner lead ends of the leads. An encapsulant is formed over the die and the electrical connections and forms a body. The strip is bent to extend vertically to a top side of the body. A lid is formed on the top side of the body and is in contact with a distal end of the vertical strip.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: May 19, 2020
    Assignee: NXP USA, Inc.
    Inventors: Lee Fee Ngion, Zi-Song Poh, Michael B. Vincent
  • Publication number: 20200131030
    Abstract: A shielded semiconductor device is assembled using a lead frame having a die receiving area, leads disposed around the die receiving area, and a bendable strip formed in the die receiving area. Each lead has an inner lead end that is spaced from but near to one of the sides of the die receiving area and an outer lead end that is distal to that side of the die receiving area. An IC die is attached to the die receiving area and electrically connected to the inner lead ends of the leads. An encapsulant is formed over the die and the electrical connections and forms a body. The strip is bent to extend vertically to a top side of the body. A lid is formed on the top side of the body and is in contact with a distal end of the vertical strip.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Inventors: Lee Fee Ngion, Zi-Song Poh, Michael B. Vincent
  • Patent number: 9209147
    Abstract: A method of forming a pillar bump includes feeding a bond wire in a capillary. The capillary has a hole portion and a chamfer section arranged downstream of the hole portion. The hole portion has a length along a feed direction of the bond wire that is greater than a maximum diameter of the hole portion. The method further includes performing an electric flame off (EFO) on a free end of the bond wire extending from the chamfer section to form a free air ball (FAB), tensioning the bond wire and applying a vacuum to the capillary to withdraw a portion of the FAB back into the capillary to substantially fill the hole portion for forming a tower, attaching the FAB to a bonding site, and at least partially removing the capillary from the bonding site and breaking the bond wire above the tower.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: December 8, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chee Seng Foong, Lee Fee Ngion, Navas Khan Oratti Kalandar, Zi Song Poh
  • Patent number: 9209144
    Abstract: A substrate for use in semiconductor device assembly has an electrically insulating body with a die mounting surface and an opposite grid array surface. An array of external electrical connection pads is located in the grid array surface. Substrate bond padsare located in the die mounting surface. Interconnects in the insulating body selectively interconnect the substrate bond padsto the external electrical connection pads. Tertiary bond pads are located in the die mounting surface and are electrically isolated from the external electrical connection pads.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: December 8, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lee Fee Ngion, Zi Song Poh