Patents by Inventor Lee Huang Chew

Lee Huang Chew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8203145
    Abstract: A semiconductor device includes a substrate having a first conductive layer disposed on a top surface of the substrate. A first insulation layer is formed over the substrate and contacts a sidewall of the first conductive layer. A second conductive layer is formed over the first insulation layer. The second conductive layer includes a first portion disposed over the first conductive layer and a second portion that extends beyond an end of the first conductive layer. A second insulation layer is formed over the second conductive layer. A first opening in the second insulation layer exposes the first portion of the second conductive layer. A second opening in the second insulation layer away from the first opening exposes the second portion of the second conductive layer. The second insulation layer is maintained around the first opening. A conductive bump is formed over the first portion of the second conductive layer.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: June 19, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Francis Heap Hoe Kuan, Byung Tai Do, Lee Huang Chew
  • Publication number: 20110121295
    Abstract: A semiconductor device includes a substrate having a first conductive layer disposed on a top surface of the substrate. A first insulation layer is formed over the substrate and contacts a sidewall of the first conductive layer. A second conductive layer is formed over the first insulation layer. The second conductive layer includes a first portion disposed over the first conductive layer and a second portion that extends beyond an end of the first conductive layer. A second insulation layer is formed over the second conductive layer. A first opening in the second insulation layer exposes the first portion of the second conductive layer. A second opening in the second insulation layer away from the first opening exposes the second portion of the second conductive layer. The second insulation layer is maintained around the first opening. A conductive bump is formed over the first portion of the second conductive layer.
    Type: Application
    Filed: February 2, 2011
    Publication date: May 26, 2011
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Francis Heap Hoe Kuan, Byung Tai Do, Lee Huang Chew
  • Patent number: 7901956
    Abstract: A semiconductor package includes a substrate having a bond pad disposed on a top surface of the substrate. A first passivation layer is formed over the substrate and bond pad. The first passivation layer has an opening to expose the bond pad. An under bump metallurgy is formed over the first passivation layer. An end of the under bump metallurgy extends beyond an end of the bond pad. A second passivation layer is formed over the under bump metallurgy. The second passivation layer has a first opening to expose a first surface of the under bump metallurgy, and a second opening which is etched to expose a second surface of the under bump metallurgy. A solder ball is attached to the first surface of the under bump metallurgy to provide electrical connectivity. The second opening in the second passivation layer receives a probe needle to test the semiconductor device.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: March 8, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Francis Heap Hoe Kuan, Byung Tai Do, Lee Huang Chew
  • Publication number: 20080042275
    Abstract: A semiconductor package includes a substrate having a bond pad disposed on a top surface of the substrate. A first passivation layer is formed over the substrate and bond pad. The first passivation layer has an opening to expose the bond pad. An under bump metallurgy is formed over the first passivation layer. An end of the under bump metallurgy extends beyond an end of the bond pad. A second passivation layer is formed over the under bump metallurgy. The second passivation layer has a first opening to expose a first surface of the under bump metallurgy, and a second opening which is etched to expose a second surface of the under bump metallurgy. A solder ball is attached to the first surface of the under bump metallurgy to provide electrical connectivity. The second opening in the second passivation layer receives a probe needle to test the semiconductor device.
    Type: Application
    Filed: August 15, 2006
    Publication date: February 21, 2008
    Inventors: Francis Heap Hoe Kuan, Byung Tai Do, Lee Huang Chew