Abstract: A latch type sense amplifier includes a latch unit, an amplifying unit and a circuit module for charging or discharging the latch unit. The latch unit is configured by two sets of serially coupled PMOS and NMOS transistors, whose gates and drains are cross-coupled. The amplifying unit is coupled between the latch unit and a complementary power supply for controlling the latch unit in response to a bit line signal and a complementary bit line signal. The circuit module is designed to charge or discharge the data storage node and the complementary data storage node of the latch unit in response to the bit line signal and the complementary bit line signal, without using a current path across the NMOS transistors therein, such that the data storage node and the complementary data storage node are charged or discharged in a manner insensitive to a mismatch between the two NMOS transistors.