Abstract: A method and system for addressing memory of an information handling system in which the memory comprises a plurality of memory banks, each of which can support a plurality of different predetermined size memory modules. The sizes of the different modules are multiples of the module having the smallest size. In the embodiment described, two different sizes are employed, a 256K capacity module and a 1 Meg. capacity module, either of which can be installed in 1 of 4 memory banks. The maximum addressable address range is therefore 4 Meg. while the minimum memory is 256K. The address range can be increased in increments of 256K corresponding to 1 segment to a total of 16 contiguous segments or 4 Meg. A memory address bus comprising 22 lines is employed in the system. The 20 low order lines address each bank simultaneously. A converter converts the 4 high order address bits 22-19 to 16 sequentially ordered segment lines.