Abstract: A jitter correcting apparatus and method for a video signal in a video signal reproduction system includes a digital video decoder for demodulating an externally-applied video signal and a phase-locked loop for generating a first clock signal synchronized with the video signal. The system includes an address generator, a comparator and a dual port memory device. The address generator generates a write address for writing the video signal in response to the first clock signal, generates a read address for reading the video signal in response to a second clock signal having a fixed frequency, and corrects the write and read addresses in response to a head switching signal and first and second comparison signals. The comparator compares the write address with the read address and generates the first comparison signal and the second comparison signal according to a result of the comparison.

Abstract: A jitter correcting apparatus and method for a video signal in a video signal reproduction system includes a digital video decoder for demodulating an externally-applied video signal and a phase-locked loop for generating a first clock signal synchronized with the video signal. The system includes an address generator, a comparator and a dual port memory device. The address generator generates a write address for writing the video signal in response to the first clock signal, generates a read address for reading the video signal in response to a second clock signal having a fixed frequency, and corrects the write and read addresses in response to a head switching signal and first and second comparison signals. The comparator compares the write address with the read address and generates the first comparison signal and the second comparison signal according to a result of the comparison.

Abstract: A jitter correcting apparatus and method for a video signal in a video signal reproduction system includes a digital video decoder for demodulating an externally-applied video signal and a phase-locked loop for generating a first clock signal synchronized with the video signal. The system includes an address generator, a comparator and a dual port memory device. The address generator generates a write address for writing the video signal in response to the first clock signal, generates a read address for reading the video signal in response to a second clock signal having a fixed frequency, and corrects the write and read addresses in response to a head switching signal and first and second comparison signals. The comparator compares the write address with the read address and generates the first comparison signal and the second comparison signal according to a result of the comparison.