Patents by Inventor Lee Kong Yu

Lee Kong Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE INCLUDING EMBEDDED MEMORY DIES AND METHOD OF MAKING SAME
    Publication number: 20230411340
    Abstract: A semiconductor device includes a signal carrier medium such as a PCB substrate having first and second opposed surfaces and a cavity formed in the second surface. A first set of one or more semiconductor dies are mounted on the first surface, and a second set of one or more semiconductor dies are mounted within the cavity. The first and/or second sets of semiconductor dies may be memory dies.
    Type: Application
    Filed: May 17, 2022
    Publication date: December 21, 2023
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Lee Kong Yu, Yoong Tatt Chin, Kim Lee Bock, Paramjeet Gill, Wei Chiat Teng, Chong Un Tan
  • System and method to enhance reliability in connection with arrangements including circuits
    Patent number: 11264301
    Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 1, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
  • System and method to enhance solder joint reliability
    Patent number: 11094604
    Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 17, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
  • System and Method to Enhance Solder Joint Reliability
    Publication number: 20200219787
    Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
    Type: Application
    Filed: March 17, 2020
    Publication date: July 9, 2020
    Inventors: Lee Kong YU, Sungjun IM, Chun Sean LAU, Yoong Tatt CHIN, Paramjeet Singh GILL, Weng-Hong TEH
  • System and method to enhance solder joint reliability
    Patent number: 10636722
    Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
  • SYSTEM AND METHOD TO ENHANCE SOLDER JOINT RELIABILITY
    Publication number: 20190326194
    Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 24, 2019
    Inventors: Lee Kong YU, Sungjun IM, Chun Sean LAU, Yoong Tatt CHIN, Paramjeet Singh GILL, Weng-Hong TEH
  • SYSTEM AND METHOD TO ENHANCE SOLDER JOINT RELIABILITY
    Publication number: 20190096783
    Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 28, 2019
    Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh