Abstract: A system comprising a system under test (SUT) having a control logic. The SUT further comprises testing logic coupled to the SUT and adapted to provide to the SUT a clock signal to facilitate communications between the testing logic and the SUT. The control logic monitors a number of activated processors in a scan chain coupled to the control logic. If the number of activated processors is reduced, the control logic dynamically decreases a frequency of the clock signal.

Abstract: A system comprising a system under test (SUT) having a control logic. The SUT further comprises testing logic coupled to the SUT and adapted to provide to the SUT a clock signal to facilitate communications between the testing logic and the SUT. The control logic monitors a number of activated processors in a scan chain coupled to the control logic. If the number of activated processors is reduced, the control logic dynamically decreases a frequency of the clock signal.

Abstract: An emulation unit/target processor interface apparatus senses the target processor I/O voltages using filters to reduce the noise level and provides the rest of the interface apparatus with a target reference voltage level. The reference voltage is used to create threshold voltages, termination voltages and drive levels appropriate to provide an interface with the target processor. Power loss in the target processor is also detected so that drive signals can be removed from the target processor to avoid damaging the target processor and to prevent the target processor from being energized by the emulation unit.

Abstract: In plurality of series-coupled circuit boards, a thermometer code is used to provide the address signals for the circuit board. Each terminal of the circuit board input connector is coupled next successive terminal of the circuit board output connector. The terminals of the circuit board input connectors are coupled, through a pull-up resistor, to a voltage source. The least significant terminal of the output terminal can provide a logic signal opposite to the logic signal provided by the voltage source. The address lines for the circuit board are coupled to the terminals of the input connector. In this manner a thermometer address code can be provided for the sequence of series-coupled circuit boards. According to the present invention, the thermometer codes can be expanded with selected additional apparatus.

Abstract: In a JTAG test and debug environment, the signal groups may have a variable length, a fixed length of a combination of both fixed and variable signal groups to be transferred to the target processor. To implement the three types of data transfers, the storage unit associated with the scan control unit includes two types of storage locations, fixed signal length storage locations and variable length storage locations. The software can select the mode of data transfer and this selection is provided to the scan controller by a command.

Abstract: In a scan controller in a test and debug system using a JTAG protocol for polling for a signal value, a poll command logic unit compares the value of each logic signal received from a target processor with the value of the expected logic value. The position in the received data stream of each logic value is compared with an expected position. When the expected value and the expected position coincide, a flag is forwarded to the test and debug unit indicating a successful polling operation. A command in the command register of the scan controller enables the apparatus to continue to poll the target processing unit in the absence of the (success) flag.

Abstract: In a test and debug environment using a JTAG protocol to test a target processing unit, apparatus for multi-value polling permits a poll unit, associated with the scan controller, to determine whether one of several possible signal groups is present in the received data stream. The test and debug unit generates a series of numbers, each number corresponding to a preselected signal groups. The corresponding field in the received data stream is decoded to provide a series of output signals, each output signal corresponding to one group. The output signals of the decoder are compared to corresponding numbers of the expected value. When a signal from the decoder unit is found to correspond to one of the selected data number, the poll operation is a success.

Abstract: In a JTAG test and debug environment, the signal groups may have a variable length, a fixed length or a combination of both fixed and variable signal groups to be transferred to the target processor. To implement the three types of data transfers, the storage unit associated with the scan control unit includes two types of storage locations, fixed signal length storage locations and variable length storage locations. The software can select the mode of data transfer and this selection is provided to the scan controller by a command.

Abstract: In a JTAG test and debug environment, the parameters that are accessed by command include a delay parameter. The delay parameter prevents the subsequent command from being executed until both the original command has been executed and the clock cycles indicated by the delay parameter have been completed. Because the time delay is included as a parameter identified by the command, the delay parameter can be programmed.

Abstract: In a JTAG test and debug configuration for testing a target processor, the scan controller includes apparatus for performing the polling operation without the intervention of the test and debug unit. The test and debug unit transfers a command and an expected value to the scan controller. In response to the command and the expected value, the scan controller repeatedly polls the selected location to determine if the expected value is present. When the expected value is identified, the test and debug unit is notified. Provision is made for a timeout of the polling procedure to prevent the polling procedure from monopolizing the scan controller activity.

Abstract: In a JTAG test and debug environment, the signal groups for boundary scans can have several lengths including signal groups that are longer that the shift register out. A storage unit is provided with a plurality of storage location lengths. The boundary scan signal groups are stored in a location having a suitable storage capacity. The command that transfers the boundary scan signal group includes a parameter identifying the relevant location. The scan control unit, upon receiving the command, transfers the entire boundary scan signal group as a result this command even if several transfers through the shift register out are required.

Abstract: In a JTAG test and debug environment, a test signal group from the target processor is provided with a status field. The status field is compared with the expected status field. In response to this comparison, the fixed signal groups are stored in a first storage unit, expected signal groups are stored in a second storage unit, and other signal groups are stored in a third storage unit. The status field of the signal group transferred from the target processor permits the analysis of the transferred signal group by the test and debug unit.

Abstract: Game apparatus includes a display unit, a game hub and at least one game controller. Each console includes a local display unit. The local display unit includes display objects that are typically available only to the user of game controller. For example, in a card game, the display objects would be the cards that had been distributed to the game controller unit. The apparatus on the game controller can be used to select the display object with which the user wishes to continue the game.