Patents by Inventor Lee M. Gavens
Lee M. Gavens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11231883Abstract: A memory device includes logic to detect the last page written in multi-plane non-volatile memory. The device includes a memory array, and a storage controller. The memory array includes multiple planes and multiple word lines operable on the memory array. The storage controller is configured to divide the word lines into contiguous sub-ranges and assign a subset of the word lines to boundaries of the sub-ranges. Each word line of the subset of word lines is assigned to a page in a different one of the memory planes. The controller operates the subset of word lines to sense a page programmed or erased state from each of the memory planes in parallel.Type: GrantFiled: July 2, 2020Date of Patent: January 25, 2022Assignee: Western Digital Technologies, Inc.Inventors: Ankit Vijay Naghate, Rakshit Tikoo, Yogendra Singh Sikarwar, Ashish Singla, Arun Thandapani, Lee M Gavens
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Publication number: 20220004336Abstract: A memory device includes logic to detect the last page written in multi-plane non-volatile memory. The device includes a memory array, and a storage controller. The memory array includes multiple planes and multiple word lines operable on the memory array. The storage controller is configured to divide the word lines into contiguous sub-ranges and assign a subset of the word lines to boundaries of the sub-ranges. Each word line of the subset of word lines is assigned to a page in a different one of the memory planes. The controller operates the subset of word lines to sense a page programmed or erased state from each of the memory planes in parallel.Type: ApplicationFiled: July 2, 2020Publication date: January 6, 2022Applicant: Western Digital Technologies, Inc.Inventors: Ankit Vijay Naghate, Rakshit Tikoo, Yogendra Singh Sikarwar, Ashish Singla, Arun Thandapani, Lee M. Gavens
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Patent number: 9323662Abstract: A system and method for using virtual physical addresses in a non-volatile memory device are disclosed. The physical layout of the non-volatile memory device may have physical die that are not a power-of-2 in number. In order to advantageously use the power-of-2 die number, which enables using a power-of-2 die interleave, a virtual physical addressing scheme is used. In particular, the virtual physical addressing scheme includes virtual die and virtual blocks, wherein the virtual die are a power-of-2 in number. Further, a conversion between the virtual physical addressing scheme and the actual physical addressing scheme is provided. In this way, for certain operations of the memory device, the virtual addressing scheme is used. For other operations, such as reading from, writing to or erasing, the actual physical addressing scheme is used.Type: GrantFiled: March 11, 2013Date of Patent: April 26, 2016Assignee: SanDisk Technologies, Inc.Inventor: Lee M. Gavens
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Patent number: 9251891Abstract: A data storage device that includes a controller and a non-volatile memory may perform a method that includes comparing, in the controller, first parameter values of a first group of parameter values to second parameter values of a second group of parameter values. The second parameter values of the second group of parameter values are associated with a scheduled non-volatile memory operation. The first parameter values correspond to parameter values that are in the non-volatile memory. The method includes sending, from the controller to the non-volatile memory, a parameter value of the second group in response to determining that the parameter value differs from a corresponding parameter value of the first group.Type: GrantFiled: November 11, 2014Date of Patent: February 2, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Ken Jianhui Hu, Nian Niles Yang, Bhuvan Khurana, Lee M. Gavens, Kulachet Tanpairoj
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Patent number: 9098205Abstract: In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings.Type: GrantFiled: January 30, 2013Date of Patent: August 4, 2015Assignee: SanDisk Technologies Inc.Inventors: Chris Nga Yee Avila, Yinda Dong, Lee M. Gavens
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Publication number: 20150067436Abstract: Data to be stored in a nonvolatile memory array may be compressed in a manner that provides variable sized portions of compressed data, which is then padded to a predetermined uniform size and then stripped of padding. The encoded compressed data is sent to the memory array where it is stored in a uniform sized area that is exclusive to the encoded compressed data.Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: SANDISK TECHNOLOGIES INC.Inventors: Xinde Hu, LEE M. GAVENS
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Publication number: 20140215126Abstract: In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings.Type: ApplicationFiled: January 30, 2013Publication date: July 31, 2014Applicant: San Disk Technologies Inc.Inventors: Chris Nga Yee Avila, Yinda Dong, Lee M. Gavens
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Publication number: 20140189200Abstract: A system and method for using virtual physical addresses in a non-volatile memory device are disclosed. The physical layout of the non-volatile memory device may have physical die that are not a power-of-2 in number. In order to advantageously use the power-of-2 die number, which enables using a power-of-2 die interleave, a virtual physical addressing scheme is used. In particular, the virtual physical addressing scheme includes virtual die and virtual blocks, wherein the virtual die are a power-of-2 in number. Further, a conversion between the virtual physical addressing scheme and the actual physical addressing scheme is provided. In this way, for certain operations of the memory device, the virtual addressing scheme is used. For other operations, such as reading from, writing to or erasing, the actual physical addressing scheme is used.Type: ApplicationFiled: March 11, 2013Publication date: July 3, 2014Inventor: Lee M. Gavens
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Patent number: 8713380Abstract: A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read points so that the data is read within an error budget. Once the optimal read point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget.Type: GrantFiled: April 26, 2012Date of Patent: April 29, 2014Assignee: Sandisk Technologies, Inc.Inventors: Chris Nga Yee Avila, Jianmin Huang, Lee M. Gavens, Idan Alrod
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Patent number: 8634240Abstract: Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC and estimated to represent a worst error rate among the copy it is sampling. One embodiment has the sample taken from one bit of each multi-bit memory cell of a group.Type: GrantFiled: September 1, 2010Date of Patent: January 21, 2014Assignee: Sandisk Technologies, Inc.Inventors: Lee M. Gavens, Jian Chen
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Patent number: 8468294Abstract: A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes.Type: GrantFiled: December 18, 2009Date of Patent: June 18, 2013Assignee: SanDisk Technologies Inc.Inventors: Jianmin Huang, Chris Avila, Lee M. Gavens, Steven Sprouse, Sergey Anatolievich Gorobets, Neil David Hutchinson
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Patent number: 8423866Abstract: Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.Type: GrantFiled: December 18, 2009Date of Patent: April 16, 2013Assignee: SanDisk Technologies, Inc.Inventors: Gautam Ashok Dusija, Jian Chen, Chris Avila, Jianmin Huang, Lee M. Gavens
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Publication number: 20120284574Abstract: A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read points so that the data is read within an error budget. Once the optimal read point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget.Type: ApplicationFiled: April 26, 2012Publication date: November 8, 2012Inventors: Chris Nga Yee Avila, Jianmin Huang, Lee M. Gavens, Idan Alrod
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Patent number: 8144512Abstract: A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation.Type: GrantFiled: December 18, 2009Date of Patent: March 27, 2012Assignee: SanDisk Technologies Inc.Inventors: Jianmin Huang, Chris Avila, Lee M. Gavens, Neil David Hutchinson, Sergey Anatolievich Gorobets
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Publication number: 20110149650Abstract: A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Inventors: Jianmin Huang, Chris Avila, Lee M. Gavens, Neil David Hutchison, Sergey Anatolievich Gorobets
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Publication number: 20110153913Abstract: A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Inventors: Jianmin Huang, Chris Avila, Lee M. Gavens, Steven Sprouse, Sergey Anatolievich Gorobets, Neil David Hutchinson
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Publication number: 20110096601Abstract: Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC and estimated to represent a worst error rate among the copy it is sampling. One embodiment has the sample taken from one bit of each multi-bit memory cell of a group.Type: ApplicationFiled: September 1, 2010Publication date: April 28, 2011Inventors: Lee M. Gavens, Jian Chen
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Publication number: 20110099460Abstract: Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.Type: ApplicationFiled: December 18, 2009Publication date: April 28, 2011Inventors: Gautam Ashok Dusija, Jian Chen, Chris Avila, Jianmin Huang, Lee M. Gavens