Patents by Inventor Lee McFearin

Lee McFearin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10366013
    Abstract: The present disclosure relates to a system and method of managing operation of a cache memory. The system and method assign each nested task a level, and each task within a nested level an instance. Using the assigned task levels and instances, the cache management module is able to determine which cache entries to evict from cache when space is needed, and which evicted cache entries to recover upon completion of preempting tasks.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: July 30, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Lee McFearin, Sushma Wokhlu, Alan Gatherer
  • Patent number: 10042773
    Abstract: Systems and techniques for advance cache allocation are described. A described technique includes selecting a job from a plurality of jobs; selecting a processor core from a plurality of processor cores to execute the selected job; receiving a message which describes future memory accesses that will be generated by the selected job; generating a memory burst request based on the message; performing the memory burst request to load data from a memory to at least a dedicated portion of a cache, the cache corresponding to the selected processor core; and starting the selected job on the selected processor core. The technique can include performing an action indicated by a send message to write one or more values from another dedicated portion of the cache to the memory.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: August 7, 2018
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Sushma Wokhlu, Lee McFearin, Alan Gatherer, Ashish Shrivastava, Peter Yifey Yan
  • Publication number: 20170206173
    Abstract: The present disclosure relates to a system and method of managing operation of a cache memory. The system and method assign each nested task a level, and each task within a nested level an instance. Using the assigned task levels and instances, the cache management module is able to determine which cache entries to evict from cache when space is needed, and which evicted cache entries to recover upon completion of preempting tasks.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Lee McFearin, Sushma Wokhlu, Alan Gatherer
  • Publication number: 20170031829
    Abstract: Systems and techniques for advance cache allocation are described. A described technique includes selecting a job from a plurality of jobs; selecting a processor core from a plurality of processor cores to execute the selected job; receiving a message which describes future memory accesses that will be generated by the selected job; generating a memory burst request based on the message; performing the memory burst request to load data from a memory to at least a dedicated portion of a cache, the cache corresponding to the selected processor core; and starting the selected job on the selected processor core. The technique can include performing an action indicated by a send message to write one or more values from another dedicated portion of the cache to the memory.
    Type: Application
    Filed: July 28, 2015
    Publication date: February 2, 2017
    Inventors: Sushma Wokhlu, Lee McFearin, Alan Gatherer, Ashish Shrivastava, Peter Yifey Yan
  • Patent number: 7251416
    Abstract: Systems and methods for optical cross connects which switch data at a container (packet) level. In one embodiment, a plurality of optical switch edges are coupled to an optical switch core via a minimal number of optical fibers. The switch core is configured to optically switch data from an ingress edge to one of a plurality of egress edges in a nonblocking fashion. The ingress edge receives data streams and distributes the data among a plurality of container processors. Each of these container processors produces an optical signal of a different wavelength, which can then be multiplexed with others to form a multiple-wavelength optical signal that is transmitted to the switch core. The switch core then switches successive portions (containers) of the multiple-wavelength signal to the egress edges to which they are respectively destined. The respective egress edges perform the reverse of this process to form output data signals.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: July 31, 2007
    Assignee: Yotta networks, LLC
    Inventors: Lakshman S. Tamil, Glen Collier, Mitch Entezari, Allesandro Fabbri, Gopalakrishnan Hari, Justin Hunt, Quan Jiang, Bing Li, Lee McFearin, Joseph M. McQuade, Earl Ponceti, Scott A. Rothrock, Frederick A. Rush, Alexander A. Smith, David Wolf