Patents by Inventor Lee Nevill
Lee Nevill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887680Abstract: Over time, the number of write cycles required to successfully program a multi-level cell (MLC) is reduced. Since a hard-coded value does not change over the lifetime of the device, the device may perform too many verify steps at one stage of the device lifetime and wait too long to begin verification at another stage of the device lifetime, reducing performance of the device. As discussed herein, verification for higher voltage level programming is delayed until verification for lower voltage level programming reaches at least a threshold level of success instead of using a hard-coded number of verify steps to skip. As a result, the performance drawbacks associated with skipping a hard-coded number of verify cycles may not occur.Type: GrantFiled: July 26, 2022Date of Patent: January 30, 2024Assignee: Micron Technology, Inc.Inventors: Jeffrey S. McNeil, Jason Lee Nevill, Tommaso Vali
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Patent number: 11823743Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.Type: GrantFiled: May 18, 2022Date of Patent: November 21, 2023Assignee: Micron Technology, Inc.Inventors: Shannon Marissa Hansen, Fulvio Rori, Andrea D'Alessandro, Jason Lee Nevill, Chiara Cerafogli
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Publication number: 20220359025Abstract: Over time, the number of write cycles required to successfully program a multi-level cell (MLC) is reduced. Since a hard-coded value does not change over the lifetime of the device, the device may perform too many verify steps at one stage of the device lifetime and wait too long to begin verification at another stage of the device lifetime, reducing performance of the device. As discussed herein, verification for higher voltage level programming is delayed until verification for lower voltage level programming reaches at least a threshold level of success instead of using a hard-coded number of verify steps to skip. As a result, the performance drawbacks associated with skipping a hard-coded number of verify cycles may not occur.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Jeffrey S. McNeil, Jason Lee Nevill, Tommaso Vali
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Patent number: 11482298Abstract: A method of operating a memory device comprises generating a target voltage using a pump circuit of the memory device, the target voltage to be applied to a word line or pillar of a memory cell of the memory device; providing an indication of current generated by the pump circuit after the pump circuit output reaches the target voltage; and determining when the current generated by the pump circuit is greater than a specified threshold current and generating a fault indication according to the determination.Type: GrantFiled: May 29, 2020Date of Patent: October 25, 2022Assignee: Micron Technology, Inc.Inventors: Jason Lee Nevill, Preston Allen Thomson, Chi Ming Chu, Sheng-Huang Lee
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Publication number: 20220277796Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.Type: ApplicationFiled: May 18, 2022Publication date: September 1, 2022Inventors: Shannon Marissa Hansen, Fulvio Rori, Andrea D'Alessandro, Jason Lee Nevill, Chiara Cerafogli
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Patent number: 11417406Abstract: Over time, the number of write cycles required to successfully program a multi-level cell (MLC) is reduced. Since a hard-coded value does not change over the lifetime of the device, the device may perform too many verify steps at one stage of the device lifetime and wait too long to begin verification at another stage of the device lifetime, reducing performance of the device. As discussed herein, verification for higher voltage level programming is delayed until verification for lower voltage level programming reaches at least a threshold level of success instead of using a hard-coded number of verify steps to skip. As a result, the performance drawbacks associated with skipping a hard-coded number of verify cycles may not occur.Type: GrantFiled: June 22, 2020Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Jeffrey S. McNeil, Jason Lee Nevill, Tommaso Vali
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Patent number: 11355200Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.Type: GrantFiled: August 18, 2020Date of Patent: June 7, 2022Assignee: Micron Technology, Inc.Inventors: Shannon Marissa Hansen, Fulvio Rori, Andrea D'Alessandro, Jason Lee Nevill, Chiara Cerafogli
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Publication number: 20220059173Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.Type: ApplicationFiled: August 18, 2020Publication date: February 24, 2022Inventors: Shannon Marissa Hansen, Fulvio Rori, Andrea D'Alessandro, Jason Lee Nevill, Chiara Cerafogli
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Publication number: 20210398599Abstract: Over time, the number of write cycles required to successfully program a multi-level cell (MLC) is reduced. Since a hard-coded value does not change over the lifetime of the device, the device may perform too many verify steps at one stage of the device lifetime and wait too long to begin verification at another stage of the device lifetime, reducing performance of the device. As discussed herein, verification for higher voltage level programming is delayed until verification for lower voltage level programming reaches at least a threshold level of success instead of using a hard-coded number of verify steps to skip. As a result, the performance drawbacks associated with skipping a hard-coded number of verify cycles may not occur.Type: ApplicationFiled: June 22, 2020Publication date: December 23, 2021Inventors: Jeffrey S. McNeil, Jason Lee Nevill, Tommaso Vali
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Publication number: 20210375387Abstract: A method of operating a memory device comprises generating a target voltage using a pump circuit of the memory device, the target voltage to be applied to a word line or pillar of a memory cell of the memory device; providing an indication of current generated by the pump circuit after the pump circuit output reaches the target voltage; and determining when the current generated by the pump circuit is greater than a specified threshold current and generating a fault indication according to the determination.Type: ApplicationFiled: May 29, 2020Publication date: December 2, 2021Inventors: Jason Lee Nevill, Preston Allen Thomson, Chi Ming Chu, Sheng-Huang Lee
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Patent number: 8312349Abstract: The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.Type: GrantFiled: October 27, 2009Date of Patent: November 13, 2012Assignee: Micron Technology, Inc.Inventors: Cory Reche, Lee Nevill, Tim Martin
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Publication number: 20110099458Abstract: The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.Type: ApplicationFiled: October 27, 2009Publication date: April 28, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Cory Reche, Lee Nevill, Tim Martin