Abstract: This invention improves and simplifies prior art systems for automatic test generation methodologies. In this invention, combinational logic is used to prevent opposing tristate bus drivers from simultaneously providing a logic signal on a common bus during testing of an integrated circuit. The combinational logic also ensures that at most one tristate buffer is enabled at all times during testing to ensure the common bus is at either a full logical 1, logical 0, or non-driven state. By preventing opposing drive signals being applied to the common bus and thus ensuring the bus is at a full logical 1 or logical 0 state when driven, automatic test generation programs can accurately generate test vectors for the integrated circuit.