Abstract: A firmware cipher component is provided which can be configured and programmed to efficiently implement a broad range of cryptographic ciphers while accelerating their processing. This firmware cipher component allows an ASIC to support multiple cipher algorithms while accelerating the operations beyond speeds conventionally achieved by software or firmware only solutions. This system combines cryptographic specific custom instructions with hardware based data manipulation accelerators. The cryptographic specific custom instructions and hardware accelerators may support both block and stream ciphers. Thus, the system may be reconfigured, allowing the cipher algorithm to change without halting the system. Further, embedding the Firmware Programmable Cipher within an ASIC may allow future capabilities to be supported in secure applications.

Abstract: A system and method for controlling a flow of data from a network interface controller (NIC) to a host processor coupled to the NIC. Data such as IP packets are received by the NIC and may be transmitted to the host processor for further processing such as firewall processing. The NIC is in communication with the host processor using, for example, a software driver running on the host processor. The NIC may monitor the processing load on the host processor as it handles packet data received from the NIC. As the processing load increases, the NIC may begin to throttle the quantity of packets being sent to the host processor in order to avoid overloading the host processor. The throttling may be governed by a heuristic throttling function.

Abstract: A firmware cipher component is provided which can be configured and programmed to efficiently implement a broad range of cryptographic ciphers while accelerating their processing. This firmware cipher component allows an ASIC to support multiple cipher algorithms while accelerating the operations beyond speeds conventionally achieved by software or firmware only solutions. This system combines cryptographic specific custom instructions with hardware based data manipulation accelerators. The cryptographic specific custom instructions and hardware accelerators may support both block and stream ciphers. Thus, the system may be reconfigured, allowing the cipher algorithm to change without halting the system. Further, embedding the Firmware Programmable Cipher within an ASIC may allow future capabilities to be supported in secure applications.