Patents by Inventor Lee S. McCarthy

Lee S. McCarthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11933580
    Abstract: Provided herein are shaped charges for focusing a fluid mass and related methods of using the shaped charges for disruption of an explosive target with a spherical projectile. The shaped charge comprises a plastic shell having a special geometric shape configured to support a shape-conforming explosive. A cylindrical plastic body has an interior volume for containing a fluid and the plastic shell. The plastic body closed distal end has a geometric shape that is substantially matched to the shape of the plastic shell. Metal spherical projectiles having an outer layer of metal selected to have an effective density matched to the fluid provide advantageous target disruption capabilities.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: March 19, 2024
    Assignee: The United States of America as Represented by the Federal Bureau of Investigation, Department of Justice
    Inventors: Ian B. Vabnick, Lee R. Foltz, Daniel E. McCarthy, Marc J. La Belle, Michael S. Shattuck
  • Patent number: 8558285
    Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: October 15, 2013
    Assignee: The Regents of the University of California
    Inventors: Umesh K. Mishra, Lee S. McCarthy
  • Patent number: 8334151
    Abstract: An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED), wherein light passes through electrically conductive ZnO. Flat and clean surfaces are prepared for both the (Al, Ga, In)N and ZnO wafers. A wafer bonding process is then performed between the (Al, Ga, In)N and ZnO wafers, wherein the (Al, Ga, In)N and ZnO wafers are joined together and then wafer bonded in a nitrogen ambient under uniaxial pressure at a set temperature for a set duration. After the wafer bonding process, ZnO is shaped for increasing light extraction from inside of LED.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: December 18, 2012
    Assignee: The Regents of the University of California
    Inventors: Akihiko Murai, Christina Ye Chen, Daniel B. Thompson, Lee S. McCarthy, Steven P. DenBaars, Shuji Nakamura, Umesh K. Mishra
  • Publication number: 20110169050
    Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.
    Type: Application
    Filed: March 23, 2011
    Publication date: July 14, 2011
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Umesh K. Mishra, Lee S. McCarthy
  • Publication number: 20100187555
    Abstract: An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED), wherein light passes through electrically conductive ZnO. Flat and clean surfaces are prepared for both the (Al, Ga, In)N and ZnO wafers. A wafer bonding process is then performed between the (Al, Ga, In)N and ZnO wafers, wherein the (Al, Ga, In)N and ZnO wafers are joined together and then wafer bonded in a nitrogen ambient under uniaxial pressure at a set temperature for a set duration. After the wafer bonding process, ZnO is shaped for increasing light extraction from inside of LED.
    Type: Application
    Filed: April 1, 2010
    Publication date: July 29, 2010
    Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akihiko Murai, Christina Ye Chen, Daniel B. Thompson, Lee S. McCarthy, Steven P. DenBaars, Shuji Nakamura, Umesh K. Mishra
  • Patent number: 7719020
    Abstract: An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED), wherein light passes through electrically conductive ZnO. Flat and clean surfaces are prepared for both the (Al, Ga, In)N and ZnO wafers. A wafer bonding process is then performed between the (Al, Ga, In)N and ZnO wafers, wherein the (Al, Ga, In)N and ZnO wafers are joined together and then wafer bonded in a nitrogen ambient under uniaxial pressure at a set temperature for a set duration. After the wafer bonding process, ZnO is shaped for increasing light extraction from inside of LED.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: May 18, 2010
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Akihiko Murai, Christina Ye Chen, Daniel B. Thompson, Lee S. McCarthy, Steven P. DenBaars, Shuji Nakamura, Umesh K. Mishra
  • Publication number: 20090085065
    Abstract: A method for fabricating III-N semiconductor devices on the N-face of layers comprising (a) growing a III-nitride semiconductor device structure in a Ga-polar direction on a substrate, (b) attaching a Ga face of the III-nitride semiconductor device structure to a host substrate, and (c) removing the substrate to expose the N-face surface of the III-nitride semiconductor device structure. An N-polar (000-1) oriented III-nitride semiconductor device is also disclosed, comprising one or more (000-1) oriented nitride layers, each having an N-face opposite a group III-face, wherein at least one N-face is an at least partially exposed N-face, and a host substrate attached to one of the group III-faces.
    Type: Application
    Filed: March 31, 2008
    Publication date: April 2, 2009
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Umesh K. Mishra, Lee S. McCarthy, Chang Soo Suh, Siddharth Rajan
  • Publication number: 20080296617
    Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.
    Type: Application
    Filed: May 1, 2008
    Publication date: December 4, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Umesh K. Mishra, Lee S. McCarthy
  • Publication number: 20080258150
    Abstract: Structures to reduce dopant activation temperatures for ion implantation in III-N transistors, using low aluminum content layers in proximity to the conducting channel, are disclosed. A method to increase the temperature at which structures can be annealed by annealing in an active nitrogen ambient, for example, in NH3 in a metalorganic chemical vapor deposition (MOCVD) chamber, is also disclosed.
    Type: Application
    Filed: March 10, 2008
    Publication date: October 23, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Lee S. McCarthy, Umesh K. Mishra, Felix Recht, Tomas Apostol Palacios Gutierrez