Abstract: The use of a high speed cache memory may be selectively controlled when a data processing task is interrupted in response to an interrupt signal, in order to prevent the interrupt from chilling the cache when insufficient performance enhancement will be realized. Disturbing the cache memory during performance of an interrupting task is prevented, thereby increasing the hit ratio of the cache when the interrupted task is resumed. Cache control information may be incorporated into a program status vector or program status word which is loaded into a program status register on occurrence of an interrupt.

Abstract: Track misregistration between a read-back head and a previously recorded pair of tracks can cause erroneous data to be detected by the read head. It has been discovered that a prior erasure to eliminate any residual magnetization reversals occurring between and along side of the two parallel data tracks in twin track vertical recording can unexpectedly increase track misregistration tolerance by several hundreds of percents over the tolerance exhibited by twin track vertical recording having no pre-write erasure in the space between tracks and along side of the tracks. The erase before write technique may be practiced with a new read-write head structure having an E-shaped erase core aligned with the twin track read-write head and insulated from it to precede the read-write structure in the direction of relative motion between the read-write head structure and the magnetic medium.

Abstract: The improved multiplexer described herein uses split band encoding across a plurality of input ports to increase the statistical advantage for compression gains but does not require a large number of input ports to achieve its advantage.