Abstract: Improved circuits for implementing various embodiments of high performance arbiters are disclosed. In one embodiment, a late-done arbiter is implemented by combining a late-decision arbiter with a decision storage (or queue) device. In another embodiment, an arbiter implementation that extends the amount of storage available for decisions is disclosed. A decision making device such as a simple arbiter is followed by a decision storage device such as a queue or a first in first out (FIFO) register of any number of stages. The decision storage device following the arbiter allows the arbiter to report each decision as quickly as it can and to start the next decision making cycle.

Abstract: An improved approach for breaking the bit lines of a semiconductor memory device into small pieces, referred to herein as Embedded Access Trees (EATs), is introduced. Embedded Access Trees enjoy the principal advantage of the banked approach by dividing long bit lines into several smaller bit lines to decrease the effective load which a selected cell must drive. However, EATs avoid most of the limitations of the banked approach, e.g., increased size, power and complexity. In a preferred embodiment of the invention, EATs are embedded into the existing full array and do not require additional peripheral decoders, MUXes or complex and costly global routing. For a given processing technology, the present invention permits a full memory array to be subdivided into more subarrays than the banked approach, with corresponding performance improvements.

Abstract: An efficient high-speed ECL to CMOS logic converter for BiCMOS integrated circuits. In one embodiment, a differential amplifier compares an ECL input signal to an ECL reference voltage and generates a pair of complementary intermediate signals on a corresponding pair of differential output nodes. The differential amplifier has two load resistors coupled in series with a common load resistor which limits the upper voltage swing at the differential output nodes. A regenerative stage coupled to the differential output nodes switches between a partially on state and a fully on state in response to the complementary intermediate signals. A pair of inverter stages convert the complementary intermediate signals into a pair of CMOS level signals. A pair of complementary output drivers coupled to the respective complementary inverter stages provide current driving capability.

Abstract: A row select circuit for semiconductor memories is disclosed. The row select circuit includes a decoder portion and a driver portion. The decoder potion of the row select circuit includes a plurality of decoder circuits, each servicing a multiplicity of rows. Two levels of decoding are used to select a row. First, one of the plurality of decoder circuits is selected. Second, a predecoder is provided for simultaneously selecting one of the multiplicity of rows serviced by the selected decoder circuit. A single current source is used to service the multiplicity of rows associated with a particular decoder. The driver portion of the circuit includes a driver circuit for each row. Each driver includes an inverter stage, a driver stage, a clamp and a voltage reference circuit. For a selected row, the driver circuit provides ultra-fast access time. For the deselected rows, the driver circuit consumes minimal power.

Abstract: A driver circuit for use in a semiconductor memory array is disclosed. The memory array includes a plurality of the driver circuits, each used to drive a word line in the memory array. The driver circuit of the present invention includes a pull up portion and an active pull down portion. The pull up portion includes a pair of cascaded transistors arranged to pull up an output node coupled to the word line. The active pull down portion includes a pair of cascaded transistors arranged to pull down the output node coupled to the word line. A control feedback path is coupled between the output node and the active pull down portion of the driver circuit. The feedback path controls the activation of the pull down portion of the driver circuit.

Abstract: A ferroelectric motor comprises a single layer of ferroelectric material electrically excited by an array of electrical contacts and an electrical excitation source for supplying phased electrical signals to the contacts thereby creating a travelling wave of mechanical deformation in the ferroelectric layer and actuating an actuator. In alternative embodiments of the invention, the actuator may be linear or rotary. The motor may be fabricated on a single integrated circuit die, in which case the layer of ferroelectric material may be a thin film of PZT. In other embodiments a motor may comprise two dies which are sandwiched together by wafer to wafer bonding. Portions of a die may be removed to permit a linear actuator to project beyond the die.

Abstract: An electrical device comprises a three-dimensional body formed from an organic polymer and a plurality of electrical elements attached to the body. The body has a regular pattern of sockets in its surface, and the electrical elements have barbed appendages, or, alternatively, the body has appendages and the electrical elements have sockets. The elements are affixed to the body by insertion of the appendages into the sockets. Electrical connections between the electrical elements are formed by selective deposition of tungsten onto the surface of the body with a scanning laser beam. A miniature ("gnat") robot can be constructed using those constructional techniques.

Abstract: An electrostatic micromotor employs a side drive design. The stator operates in a plane above a substract and a moveable member lies and moves in the plane of the stator. An electrostatic field of operational strength is generated and sustained without breakdown in the plane between the stator and edges of the moveable member. Three fabrication processes enable formation of a moveable member in the plane of operation of the stator and spaced apart from the stator by a micron amount. One fabrication process deposits and patterns a structural layer to form the stator and moveable member over a sacrificial layer. A second fabrication process etches channels in a first structural layer to outline a stator, moveable member, and if desired, a bearing. A substrate is connected to the side of the structural layer through which the channels are etched and the opposite side is ground down to the ends of the channels to form salient stator, rotor and, if desired, bearing structures.

Abstract: An infrared sensor operable without cooling and thus usable at room temperature comprises a substrate supporting thin films of pyroelectric material and switched capacitor control circuitry. The control circuitry compares the absolute capacitance of a reference thin film to that of a sensor thin film, thereby sensing infrared radiation without the use of a chopper device. The reference thin film is thermally coupled to the substrate, and the sensor thin film is thermally insulated form the substrate. To increase the fill factor, the sensor thin film is placed directly above the control circuitry. In another apsect, the sensor is adpated to sense visible and infrared light by adding a CCD sensor and appropriate control circuitry to the substrate.