Abstract: Provide are a compound capable of improving the light-emitting efficiency, stability, and lifespan of an element, an organic electronic element using same, and an electronic device thereof.

Abstract: The present invention may provide a respiration adjustment device and a respiration measurement mouthpiece assembly including same, the device comprising: a body part in which an inlet part through which air exhaled by breathing of a user is introduced, an outlet part through which air is discharged and which is coupled to a mouthpiece, and an internal flow path are formed; and a pressure regulator provided in the internal flow path and adjusting the pressure of air through the manipulation of the user. According to the description above, a user can adjust respiratory pressure by himself or herself according to the user's health condition and thus perform a breathing exercise suitable for each individual user. Therefore, the present invention can increase an effect of the breathing exercise.

Abstract: Power distribution circuitry to improve wireless power distribution and facilitate wireless power transfer (WPT) operations in a wireless communication device under a variety of operating conditions. In various exemplary embodiments of the disclosure, the power distribution circuitry operates to provide a wireless power (WP) supply voltage to wireless communication circuitry of the device in order enable a WPT connection procedure under certain low power conditions. Such conditions might include a power off mode, a sleep mode, and dead/low battery operating conditions wherein the available battery supply voltage is less than a threshold voltage required to enable device components. The power distribution circuitry may switch the supply voltage of the wireless communication circuitry to another available supply voltage source after the WPT connection procedure is completed and wireless power is being received by the wireless communication device.

Abstract: Power distribution circuitry to improve wireless power distribution and facilitate wireless power transfer (WPT) operations in a wireless communication device under a variety of operating conditions. In various exemplary embodiments of the disclosure, the power distribution circuitry operates to provide a wireless power (WP) supply voltage to wireless communication circuitry of the device in order enable a WPT connection procedure under certain low power conditions. Such conditions might include a power off mode, a sleep mode, and dead/low battery operating conditions wherein the available battery supply voltage is less than a threshold voltage required to enable device components. The power distribution circuitry may switch the supply voltage of the wireless communication circuitry to another available supply voltage source after the WPT connection procedure is completed and wireless power is being received by the wireless communication device.

Abstract: A thin film transistor array panel for a liquid crystal display, a liquid crystal display and a manufacturing method thereof are provided. The display panel includes: a substrate; and a first electrode portion disposed on the substrate, the first electrode portion having two pairs of main edges facing each other and a first cutout oblique to the main edges, wherein the main edges include first and second edges, the first electrode portion has an oblique edge substantially parallel to the first cutout, the oblique connecting the first edge and the second edge, the first edge includes a first portion extending from the oblique edge to an end of the first cutout, and the oblique edge is substantially equal to or longer than a half of the first portion of the first edge.

Abstract: A passivation layer is deposited and a photoresist is formed. The photoresist includes first to third portions with decreased thickness, the second portions located on portions of drain electrodes and data lines and the third portions located on portions of gate lines. A mask for forming the photoresist has rectilinear slits with width and distance of about 0.8-2.0 microns on an area corresponding to the second portions. The passivation layer and an underlying semiconductor layer as well as the photoresist are etched to expose portions of the gate insulating layer under the third portions of the photoresist as well as portions of the passivation layer under the second portions of the photoresist. The exposed portions of the passivation layer and the gate insulating layer are removed to expose the drain electrodes, the gate lines and the data lines as well as portions of the semiconductor layer, which are subsequently removed.

Abstract: To improve product yield, light is scanned on a layer on a substrate through a mask. A pattern is formed on the substrate by the exposure of the layer. The direction of scanning is substantially perpendicular to a longitudinal direction of the pattern. The capacitance difference due to coupling of the pattern to be formed and a conductive layer formed through an insulation layer is reduced. Thus, failures of a display device are reduced and the product yield is increased.

Abstract: A passivation layer is deposited and a photoresist is formed. The photoresist includes first to third portions with decreased thickness, the second portions located on portions of drain electrodes and data lines and the third portions located on portions of gate lines. A mask for forming the photoresist has rectilinear slits with width and distance of about 0.8-2.0 microns on an area corresponding to the second portions. The passivation layer and an underlying semiconductor layer as well as the photoresist are etched to expose portions of the gate insulating layer under the third portions of the photoresist as well as portions of the passivation layer under the second portions of the photoresist. The exposed portions of the passivation layer and the gate insulating layer are removed to expose the drain electrodes, the gate lines and the data lines as well as portions of the semiconductor layer, which are subsequently removed.

Abstract: An analog/mixed-signal DFT/BIST test module for use in a semiconductor tester to support DFT/BIST testing of semiconductor devices having at least one analog/mixed-signal circuit-under-test is disclosed. The analog/mixed-signal circuit-under-test coupled to an on-chip test circuit having a test signal input and a test signal output. The analog/mixed-signal DFT/BIST test module includes signal source circuitry for generating test signals for application to the test signal input of the analog/mixed-signal circuit-under-test and capture circuitry for acquiring output signals from the test signal output of the analog/mixed-signal circuit-under-test. Processing circuitry responsive to user-programmed algorithms analyzes the output signals from the analog/mixed-signal circuit under test independent of the semiconductor tester host computer.

Abstract: Disclosed herein is a composition for use as a film on an image display filter. In some embodiments, the composition includes a cyanine dye exhibiting an absorption maximum in the wavelength region from about 830 to about 880 nm or from about 580 to about 600 nm and an anthraquinone dye comprising an anthraquinone compound substituted with an amino group in one or more positions selected from the 1-, 4-, 5-, and 8-position.

Abstract: Disclosed herein is a low-reflectivity, brightness-enhancing multilayer optical film for enhancing the brightness of an organic light emission diode (OLED) display and imparting anti-reflection performance to the display. The multilayer optical film comprises a transparent substrate, a light diffusion layer formed on the transparent substrate by wet coating and a light-absorbing layer formed on the light diffusion layer by wet coating wherein the substrate has a thickness of 10˜300 ?m, the light diffusion layer contains a resin and spherical particles, and the light-absorbing layer contains 50˜500 parts by weight of core-shell structured light-absorbing particles composed of a light-absorbing agent as a material for the core and a transparent resin as a material for the shell. Further disclosed is an organic light emitting diode (OLED) display using the multilayer optical film.

Abstract: A thin film transistor array panel for a liquid crystal display, a liquid crystal display and a manufacturing method thereof are provided. The display panel includes: a substrate; and a first electrode portion disposed on the substrate, the first electrode portion having two pairs of main edges facing each other and a first cutout oblique to the main edges, wherein the main edges include first and second edges, the first electrode portion has an oblique edge substantially parallel to the first cutout, the oblique connecting the first edge and the second edge, the first edge includes a first portion extending from the oblique edge to an end of the first cutout, and the oblique edge is substantially equal to or longer than a half of the first portion of the first edge.

Abstract: A liquid crystal display includes a pixel electrode, a common electrode facing the pixel electrode, and a thin film transistor including a gate electrode connected to a gate line, a source electrode connected to a data line, and a drain electrode connected to the pixel electrode. First and second domain defining members defining domains are provided at the liquid crystal display and the drain electrode is disposed near a corner of one of the domains. The drain electrode has an edge extending perpendicular to major edges of the domains and located closest to a center of the one of the domains.

Abstract: To improve product yield, light is scanned on a layer on a substrate through a mask. A pattern is formed on the substrate by the exposure of the layer. The direction of scanning is substantially perpendicular to a longitudinal direction of the pattern. The capacitance difference due to coupling of the pattern to be formed and a conductive layer formed through an insulation layer is reduced. Thus, failures of a display device are reduced and the product yield is increased.

Abstract: A passivation layer is deposited and a photoresist is formed. The photoresist includes first to third portions with decreased thickness, the second portions located on portions of drain electrodes and data lines and the third portions located on portions of gate lines. A mask for forming the photoresist has rectilinear slits with width and distance of about 0.8-2.0 microns on an area corresponding to the second portions. The passivation layer and an underlying semiconductor layer as well as the photoresist are etched to expose portions of the gate insulating layer under the third portions of the photoresist as well as portions of the passivation layer under the second portions of the photoresist. The exposed portions of the passivation layer and the gate insulating layer are removed to expose the drain electrodes, the gate lines and the data lines as well as portions of the semiconductor layer, which are subsequently removed.

Abstract: A liquid crystal display includes a pixel electrode, a common electrode facing the pixel electrode, and a thin film transistor including a gate electrode connected to a gate line, a source electrode connected to a data line, and a drain electrode connected to the pixel electrode. First and second domain defining members defining domains are provided at the liquid crystal display and the drain electrode is disposed near a corner of one of the domains. The drain electrode has an edge extending perpendicular to major edges of the domains and located closest to a center of the one of the domains.

Abstract: An RF transponder having an antenna comprising at least two ports operable to receive signals such that, in use, the signals in combination establish at least two current nulls on the antenna, each of the ports being located substantially at a current null.

Abstract: An analog/mixed-signal DFT/BIST test module for use in a semiconductor tester to support DFT/BIST testing of semiconductor devices having at least one analog/mixed-signal circuit-under-test is disclosed. The analog/mixed-signal circuit-under-test coupled to an on-chip test circuit having a test signal input and a test signal output. The analog/mixed-signal DFT/BIST test module includes signal source circuitry for generating test signals for application to the test signal input of the analog/mixed-signal circuit-under-test and capture circuitry for acquiring output signals from the test signal output of the analog/mixed-signal circuit-under-test. Processing circuitry responsive to user-programmed algorithms analyzes the output signals from the analog/mixed-signal circuit under test independent of the semiconductor tester host computer.