Patents by Inventor Lee Sun Lim

Lee Sun Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055374
    Abstract: A semiconductor device has a semiconductor substrate and first insulating layer formed over the surface of the semiconductor substrate. A dummy via is formed through the first insulating layer. A second insulating layer is formed over the first insulating layer to fill the dummy via. A first conductive layer is formed over the second insulating layer. A bump is formed over the first conductive layer adjacent to the dummy via filled with the second insulating layer. A second conductive layer is formed over a surface of the semiconductor substrate. The dummy via filled with the second insulating layer relieves stress on the second conductive layer. A plurality of dummy vias filled with the second insulating layer can be formed within a designated via formation area. A plurality of dummy vias filled with the second insulating layer can be formed in a pattern.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 15, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Peik Eng Ooi, Lee Sun Lim
  • Patent number: 9620557
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: April 11, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xu Sheng Bao, Ma Phoo Pwint Hlaing
  • Publication number: 20160104731
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Application
    Filed: December 18, 2015
    Publication date: April 14, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xu Sheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: 9252172
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xusheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: 9171769
    Abstract: A semiconductor device has a plurality of semiconductor die mounted active surface to a carrier. An encapsulant is deposited over semiconductor die and carrier. Openings are formed through a surface of the encapsulant to divide the encapsulant into discontinuous segments. The openings have straight or beveled sidewalls. The openings can be formed partially through the surface of the encapsulant in an area between the semiconductor die. The openings can be formed partially through the surface of the encapsulant over the semiconductor die. The openings can be formed through the encapsulant in an area between the semiconductor die. A portion of the surface of the encapsulant is removed down to a bottom of the openings. The carrier is removed. An interconnect structure is formed over the encapsulant and the semiconductor die. The encapsulant is cured prior to or after forming the openings.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: October 27, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xusheng Bao, Ma Phoo Pwint Hlaing
  • Publication number: 20120306038
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xusheng Bao, Ma Phoo Pwint Hlaing
  • Publication number: 20120139120
    Abstract: A semiconductor device has a plurality of semiconductor die mounted active surface to a carrier. An encapsulant is deposited over semiconductor die and carrier. Openings are formed through a surface of the encapsulant to divide the encapsulant into discontinuous segments. The openings have straight or beveled sidewalls. The openings can be formed partially through the surface of the encapsulant in an area between the semiconductor die. The openings can be formed partially through the surface of the encapsulant over the semiconductor die. The openings can be formed through the encapsulant in an area between the semiconductor die. A portion of the surface of the encapsulant is removed down to a bottom of the openings. The carrier is removed. An interconnect structure is formed over the encapsulant and the semiconductor die. The encapsulant is cured prior to or after forming the openings.
    Type: Application
    Filed: December 6, 2010
    Publication date: June 7, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xusheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: 8110913
    Abstract: An integrated circuit package system includes: fabricating a lead frame including: providing inner leads having an inner lead pitch of progressive length, forming a lead shoulder, on the inner leads, having a shoulder height of a progressive height, and forming outer leads coupled to the lead shoulder and the inner leads; mounting an integrated circuit die on the lead frame; and molding a package body on the lead frame and the integrated circuit die.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: February 7, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Linda Pei Ee Chua, Zheng Zheng, Lee Sun Lim
  • Publication number: 20090001531
    Abstract: An integrated circuit package system includes: fabricating a lead frame including: providing inner leads having an inner lead pitch of progressive length, forming a lead shoulder, on the inner leads, having a shoulder height of a progressive height, and forming outer leads coupled to the lead shoulder and the inner leads; mounting an integrated circuit die on the lead frame; and molding a package body on the lead frame and the integrated circuit die.
    Type: Application
    Filed: June 24, 2008
    Publication date: January 1, 2009
    Inventors: Byung Tai Do, Linda Pei Ee Chua, Zheng Zheng, Lee Sun Lim