Patents by Inventor Lee Teck Yeow

Lee Teck Yeow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vertical ball grid array integrated circuit package
    Patent number: 6420782
    Abstract: An integrated circuit package (30, 32) for vertical attachment as part of a high density module (200) comprising a carrier (70) having an opening (86), routing strips (82), conduits (84) and side surface terminals (100), the side surface terminals (100) disposed on a side surface (92), which side surface is common to the carrier (70) and the integrated circuit package 30, 32. An adhesive layer (60), which attaches a silicon chip (50) to a carrier (70), wire bonding (80) electrically connecting the silicon chip (50) to the routing strips (82) and potting material (90) filling the opening (86), are also disclosed.
    Type: Grant
    Filed: January 6, 2000
    Date of Patent: July 16, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Kian Teng Eng, Lee Teck Yeow
  • Die pad for integrated circuits
    Publication number: 20020070436
    Abstract: Die pads are provided which reduce moisture retention and thermal mismatch by employing a number of die pad sections or a die pad support portion with a number of relief regions. In each case, the die pad area to die area ratio is reduced to improve the thermal mismatch between the die and the die pad. Also, the die pad sections or relief regions are arranged in a spaced apart fashion to provide moisture escape paths between the die and the die pad.
    Type: Application
    Filed: October 18, 2001
    Publication date: June 13, 2002
    Inventors: Chong Chin Hui, Lee Teck Yeow, Chen Fung Leng, Rahul Kapoor
  • Vertical ball grid array integrated circuit package
    Publication number: 20010042910
    Abstract: An integrated circuit package (30, 32) for vertical attachment as part of a high density module (200) comprising a carrier (70) having an opening (86), routing strips (82), conduits (84) and side surface terminals (100), the side surface terminals (100) disposed on a side surface (92), which side surface is common to the carrier (70) and the integrated circuit package 30, 32. An adhesive layer (60), which attaches a silicon chip (50) to a carrier (70), wire bonding (80) electrically connecting the silicon chip (50) to the routing strips (82) and potting material (90) filling the opening (86), are also disclosed.
    Type: Application
    Filed: January 19, 2001
    Publication date: November 22, 2001
    Inventors: Klan Teng Eng, Lee Teck Yeow
  • Vertical ball grid array integrated circuit package
    Patent number: 6320126
    Abstract: An integrated circuit package (30, 32) for vertical attachment as part of a high density module (200) having a carrier (70) having an opening (86), routing strips (82), conduits (84) and side surface terminals (100), the side surface terminals (100) disposed on a side surface (92), which side surface is common to the carrier (70) and the integrated circuit package 30, 32. An adhesive layer (60), which attaches a silicon chip (50) to a carrier (70), wire bonding (80) electrically connecting the silicon chip (50) to the routing strips (82) and potting material (90) filling the opening (86), are also disclosed.
    Type: Grant
    Filed: July 14, 1998
    Date of Patent: November 20, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Kian Teng Eng, Lee Teck Yeow