Abstract: A method and apparatus for attaching a module such as a semiconductor device, having an array of contacts arranged thereon in a given pattern to a substrate such as a printed circuit board comprises applying an array of solder blocks to the array of contacts on the module. The module is then positioned on the substrate so that the array of solder blocks contacts the array of contact pads on the substrate. Heat is then applied to reflow the solder blocks to provide mechanical and electrical connection of the module to the substrate.

Abstract: Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.

Abstract: A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen to produce a desired amount of stress to improve device performance. In an example embodiment for a tensile stress layer, the PMOS S/D contact area is larger than the NMOS S/D contact area so the tensile stress on the PMOS channel is less than the tensile stress on the NMOS channel. In an example embodiment for a compressive stress layer, the NMOS contact area is larger than the PMOS contact area so that the compressive stress on the NMOS channel is less than the compressive stress on the PMOS channel.

Abstract: A structure and a method of manufacturing a memory devices using nanoncrystals. A first embodiment is characterized as follows. We form a first gate insulator over the substrate. The first gate insulator is comprised of an oxide layer and blocking layer. We form a SiGe layer over the first gate insulator layer. Then we perform an oxidation/anneal process consume the SiGe layer to form Ge nanocrystals7 on the first gate insulator layer and a silicon oxide layer over the first gate insulator layer. We form a gate electrode over the a silicon oxide layer. In a second embodiment, the first gate insulator is comprised of one layer of oxidation blocking material. The blocking layer prevents the oxidation of the substrate during process steps used to form the nanocrystals.

Abstract: Devices with embedded silicon or germanium nanocrystals, fabricated using ion implantation, exhibit superior data-retention characteristics relative to conventional floating-gate devices. However, the prior art use of ion implantation for their manufacture introduces several problems. These have been overcome by initial use of rapid thermal oxidation to grow a high quality layer of thin tunnel oxide. Chemical vapor deposition is then used to deposit a germanium doped oxide layer. A capping oxide is then deposited following which the structure is rapid thermally annealed to synthesize the germanium nanocrystals.