Patents by Inventor Lee Tsung Hsiung
Lee Tsung Hsiung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9385731Abstract: A phase-locked loop (PLL) is provided. The PLL comprises a clock adjuster configured to receive an initial clock signal having an initial frequency and a mode control signal. The clock adjuster is configured to modify the initial clock signal into a modified clock signal based on the mode control signal. The PLL is configured such that a loop bandwidth is equal to a specified bandwidth. When the modified clock signal is changed, a loop gain of a loop filter is adjusted such that the loop bandwidth is substantially equal to the specified bandwidth. When the modified clock signal is changed, an oscillator tuning word (OTW) signal is modified into a normalized OTW signal such that the loop bandwidth is substantially equal to the specified bandwidth.Type: GrantFiled: July 16, 2014Date of Patent: July 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Feng Wei Kuo, Kuang-Kai Yen, Huan-Neng Chen, Lee Tsung Hsiung, Chewn-Pu Jou, Robert Bogdan Staszewski
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Patent number: 9319053Abstract: A phase-locked loop (PLL) is provided. The PLL comprises a dithering circuit that is configured to receive a second tuning signal, and dither the second tuning signal to generate a dither signal to decrease a magnitude of a spur of the PLL. The dither signal is used by a digitally controlled oscillator (DCO) to generate an output signal of the PLL. Operation of the dithering circuit is controlled using a spur-cancel control circuit. The spur-cancel control circuit receives a frequency command word (FCW) signal and determines a value of an enable signal based on the FCW signal. In some embodiments, the dithering circuit dithers the second tuning signal based on the enable signal.Type: GrantFiled: July 18, 2014Date of Patent: April 19, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Feng Wei Kuo, Kuang-Kai Yen, Huan-Neng Chen, Lee Tsung Hsiung, Chewn-Pu Jou, Robert Bogdan Staszewski
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Publication number: 20160020775Abstract: A phase-locked loop (PLL) is provided. The PLL comprises a clock adjuster configured to receive an initial clock signal having an initial frequency and a mode control signal. The clock adjuster is configured to modify the initial clock signal into a modified clock signal based on the mode control signal. The PLL is configured such that a loop bandwidth is equal to a specified bandwidth. When the modified clock signal is changed, a loop gain of a loop filter is adjusted such that the loop bandwidth is substantially equal to the specified bandwidth. When the modified clock signal is changed, an oscillator tuning word (OTW) signal is modified into a normalized OTW signal such that the loop bandwidth is substantially equal to the specified bandwidth.Type: ApplicationFiled: July 16, 2014Publication date: January 21, 2016Inventors: Feng Wei Kuo, Kuang-Kai Yen, Huan-Neng Chen, Lee Tsung Hsiung, Chewn-Pu Jou, Robert Bogdan Staszewski
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Publication number: 20160020776Abstract: A phase-locked loop (PLL) is provided. The PLL comprises a dithering circuit that is configured to receive a second tuning signal, and dither the second tuning signal to generate a dither signal to decrease a magnitude of a spur of the PLL. The dither signal is used by a digitally controlled oscillator (DCO) to generate an output signal of the PLL. Operation of the dithering circuit is controlled using a spur-cancel control circuit. The spur-cancel control circuit receives a frequency command word (FCW) signal and determines a value of an enable signal based on the FCW signal. In some embodiments, the dithering circuit dithers the second tuning signal based on the enable signal.Type: ApplicationFiled: July 18, 2014Publication date: January 21, 2016Inventors: Feng Wei Kuo, Kuang-Kai Yen, Huan-Neng Chen, Lee Tsung Hsiung, Chewn-Pu Jou, Robert Bogdan Staszewski
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Patent number: 8884670Abstract: One or more techniques or systems for locking a phase locked loop (PLL) are provided herein. In some embodiments, a multi-phase time-to-digital converter (TDC) includes a first phase finder, a phase predictor, a second phase finder, and a phase switch. For example, the first phase finder is configured to generate a first fractional phase signal based on a multi-phase variable clock (CKV) signal. For example, the phase predictor is configured to generate a phase select (QSEL) signal or a multi-phase CKV select (CKVSEL) signal based on a frequency command word (FCW) signal or the multi-phase CKV signal. For example, the second phase finder is configured to generate a second fractional phase signal based on the CKVSEL signal or the QSEL signal. For example, the phase switch is configured to select the first or second fractional phase signal based on a phase error (PHE) signal.Type: GrantFiled: November 25, 2013Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kuang-Kai Yen, Feng Wei Kuo, Huan-Neng Chen, Lee Tsung Hsiung, Hsien-Yuan Liao, Robert Bogdan Staszewski, Chewn-Pu Jou
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Publication number: 20140210528Abstract: One or more techniques or systems for locking a phase locked loop (PLL) are provided herein. In some embodiments, a multi-phase time-to-digital converter (TDC) includes a first phase finder, a phase predictor, a second phase finder, and a phase switch. For example, the first phase finder is configured to generate a first fractional phase signal based on a multi-phase variable clock (CKV) signal. For example, the phase predictor is configured to generate a phase select (QSEL) signal or a multi-phase CKV select (CKVSEL) signal based on a frequency command word (FCW) signal or the multi-phase CKV signal. For example, the second phase finder is configured to generate a second fractional phase signal based on the CKVSEL signal or the QSEL signal. For example, the phase switch is configured to select the first or second fractional phase signal based on a phase error (PHE) signal.Type: ApplicationFiled: November 25, 2013Publication date: July 31, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kuang-Kai Yen, Feng Wei Kuo, Huan-Neng Chen, Lee Tsung Hsiung, Hsien-Yuan Liao, Robert Bogdan Staszewski, Chewn-Pu Jou
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Patent number: 8593189Abstract: One or more techniques or systems for locking a phase locked loop (PLL) are provided herein. In some embodiments, a multi-phase time-to-digital converter (TDC) includes a first phase finder, a phase predictor, a second phase finder, and a phase switch. For example, the first phase finder is configured to generate a first fractional phase signal based on a multi-phase variable clock (CKV) signal. For example, the phase predictor is configured to generate a phase select (QSEL) signal or a multi-phase CKV select (CKVSEL) signal based on a frequency command word (FCW) signal or the multi-phase CKV signal. For example, the second phase finder is configured to generate a second fractional phase signal based on the CKVSEL signal or the QSEL signal. For example, the phase switch is configured to select the first or second fractional phase signal based on a phase error (PHE) signal.Type: GrantFiled: January 31, 2013Date of Patent: November 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kuang-Kai Yen, Feng Wei Kuo, Huan-Neng Chen, Lee Tsung Hsiung, Hsien-Yuan Liao, Robert Bogdan Staszewski
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Patent number: 8570082Abstract: The present disclosure relates to an all digital phase locked loop (APDLL) that can account for variations in PVT conditions, and a related method of formation. In some embodiments, the ADPLL has a controllable time-to-digital converter (TDC) having a plurality of variable delay elements. The controllable TDC is determines a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a phase error therefrom. A digitally controlled oscillator (DCO) varies a phase of the local oscillator clock signal based upon the phase error. A calibration unit determines an effect of variations in PVT (process, voltage, and temperature) conditions based upon the phase error and to generate a TDC tuning word that adjusts a delay introduced by one or more of the plurality of variable delay elements to account for the variations in PVT conditions.Type: GrantFiled: February 27, 2013Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng Wei Kuo, Kuang-Kai Yen, Huan-Neng Chen, Hsien-Yuan Liao, Lee Tsung Hsiung, Chewn-Pu Jou, Robert Bogdan Staszewski