Abstract: A signal processor architecture that comprises a data network having multiple ports, a control bus, and a plurality of signal processing clusters connected to at least two ports and the control bus. Each signal processing cluster comprises a system control processor connected to the control bus, a second control bus, and a global bulk memory having multiple ports. A plurality of functional processing elements are connected to the system control processor by way of the second control bus, and each are connected to a port of the global bulk memory. The global bulk memory comprises a subdata flow network having multiple gateways and full crossbar interconnectivity between each of the multiple gateways.

Abstract: A dense modular system for the high speed computation of a composite fast Fourier transform (FFT) is disclosed. The composite FFT is formed by aggregating a series of individual FFT passes. The FFT passes are calculated within module boundaries in a substantially parallel manner and the input and output between the modules is transmitted in a substantially serial manner. The serial transmission takes place at a higher speed than the parallel FFT computation in order to preserve the constant data flow in the composite FFT.

Abstract: Control for overlapping instruction execution in an arithmetic unit is provided by stepping a sequence of instructions through a plurality of registers connected in cascade and separately decoding each instruction in a register for control of a corresponding stage in one or more data processing paths, each comprising stages through which data being processed is stepped, each stage corresponding to only one register of the control pipeline. The output of the decoder of each instruction register controls the required operations in the corresponding stage of the data pipeline. Automatically indexed indirect addressing is provided by use of pointers for data sources and destinations as required in the execution of every instruction in order to facilitate highly iterative and structured operations on blocks or arrays of data.

Abstract: Control for overlapping instruction execution in an arithmetic unit is provided by stepping a sequence of instructions through a plurality of registers connected in cascade and separately decoding each instruction in a register for control of a corresponding stage in one or more data processing paths, each comprising stages through which data being processed is stepped, each stage corresponding to only one register of the control pipeline. The output of the decoder of each instruction register controls the required operations in the corresponding stage of the data pipeline. Automatically indexed indirect addressing is provided by use of pointers for data sources and destinations as required in the execution of every instruction in order to facilitate highly iterative and structured operations on blocks or arrays of data.