Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: A transistor includes a substrate and a gate over the substrate. The transistor further includes a source and a drain over the substrate on opposite sides of the gate. The transistor further includes a channel region beneath the gate separating the source from the drain, the channel region having a channel width with respect to a surface of the substrate greater than a width of the gate with respect to the surface of the substrate. The transistor further includes a silicide over a first portion of the drain, wherein a second portion of the drain, closer to the gate than the first portion, is an unsilicided region.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: A method of preventing contact metal from protruding into neighboring gate devices to affect work functions of the neighboring gate devices is provided includes forming a gate structure. Forming the gate structure includes forming a work function layer, and forming a gate metal layer having a void, wherein the work function layer surrounds the gate metal layer. The method further includes forming a contact plug having a contact metal directly on the gate metal layer of the first gate stack, wherein the contact metal protrudes into the void, and the work function layer prevents the contact metal from protruding into a second gate stack.

Abstract: A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width. Each gate electrode of the first set of gate electrodes has a first gate width. The method further includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width. Each gate electrode of the second set of gate electrodes has a second gate width greater than the first gate width.

Abstract: A method includes providing a semiconductor substrate having an active region and forming an isolation structure to isolate the active region. First and second gate structures are formed over the active region. First and second doped regions are formed within the active region of the substrate, the first doped region has a first conductivity type, the second doped region has the second conductivity type. The first and second gate structures are interposed between the first and second doped regions.

Abstract: The present disclosure provides a semiconductor device having a transistor. The transistor includes a source region, a drain region, and a channel region that are formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The transistor includes a first gate that is disposed over the channel region. The transistor includes a plurality of second gates that are disposed over the drain region.

Abstract: A method for fabricating a field-effect transistor includes forming a spacer adjacent to sidewalls of a gate structure. The method further includes forming silicide regions in a substrate adjacent to the spacer. The method further includes depositing a first interlayer dielectric layer over the substrate. The method further includes exposing a top surface of the gate structure. The method further includes depositing a contact etch stop layer over the first interlayer dielectric layer and the top surface of the gate structure. The method further includes patterning the contact etch stop layer to remove a portion of the contact etch stop layer over the silicide regions, wherein the contact etch stop layer over the gate structure is maintained.

Abstract: An integrated circuit includes a semiconductor substrate; a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate. The first width is less than the second width. The first STI feature has an etch-resistance less than that of the second STI feature.

Abstract: A transistor includes a substrate and a gate over the substrate. The transistor further includes a source and a drain over the substrate on opposite sides of the gate. The transistor further includes a channel region beneath the gate separating the source from the drain, the channel region having a channel width with respect to a surface of the substrate greater than a width of the gate with respect to the surface of the substrate. The transistor further includes a silicide over a first portion of the drain, wherein a second portion of the drain, closer to the gate than the first portion, is an unsilicided region.