Abstract: A rechargeable battery is disclosed. The rechargeable battery of the invention includes a high density capacitor and an integrated circuit. The high density capacitor is connected to a ground terminal and a first node carrying a first voltage. The integrated circuit includes a band gap circuit, a first detecting unit, a voltage divider, a second detecting unit and at least one low dropout voltage regulator. The band gap circuit generates a band gap voltage according to the first voltage. The first detecting unit measures the first voltage and determines whether to apply an input charging voltage to the high density capacitor. The voltage divider is connected in parallel with the high density capacitor and has a second node carrying a second voltage. The second detecting unit measures the second voltage according to the band gap voltage and determines whether to connect a third node to the first node.

Abstract: A rechargeable battery is disclosed. The rechargeable battery of the invention includes a high density capacitor and an integrated circuit. The high density capacitor is connected to a ground terminal and a first node carrying a first voltage. The integrated circuit includes a band gap circuit, a first detecting unit, a voltage divider, a second detecting unit and at least one low dropout voltage regulator. The band gap circuit generates a band gap voltage according to the first voltage. The first detecting unit measures the first voltage and determines whether to apply an input charging voltage to the high density capacitor. The voltage divider is connected in parallel with the high density capacitor and has a second node carrying a second voltage. The second detecting unit measures the second voltage according to the band gap voltage and determines whether to connect a third node to the first node.

Abstract: The structures and methods of reading out semiconductor Non-Volatile Memory (NVM) using referencing cells are disclosed. The new invented scheme can reduce large current consumption from the direct current biasing in the conventional scheme and achieve a high resolution on the cell threshold voltage with a good sensing speed.

Abstract: A method for erasing a flash EEPROM memory device is disclosed. The memory device has a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics.

Abstract: A method for erasing a flash EEPROM memory device is disclosed. The memory device has a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics.

Abstract: The structures and methods of reading out semiconductor Non-Volatile Memory (NVM) using referencing cells are disclosed. The new invented scheme can reduce large current consumption from the direct current biasing in the conventional scheme and achieve a high resolution on the cell threshold voltage with a good sensing speed.

Abstract: A method of trimming FET NVM cells in Multi-Level-Cell (MLC) operation is provided. The method comprises (a) applying a first voltage and a second voltage to a control gate and a bulk of the over-programmed FET NVM cell, respectively; and (b) applying a signal to a drain of the over-programmed FET NVM cell for a time period to produce a limited threshold voltage reduction; wherein polarities of the first voltage and the second voltage are opposite to that of the signal. Thus, the charge placement in the storing material could be precisely controlled within a small range of charge state and produce a multi-bits/cell of higher digital storage density.

Abstract: A method of trimming FET NVM cells in Multi-Level-Cell (MLC) operation is provided. The method comprises (a) applying a first voltage and a second voltage to a control gate and a bulk of the over-programmed FET NVM cell, respectively; and (b) applying a signal to a drain of the over-programmed FET NVM cell for a time period to produce a limited threshold voltage reduction; wherein polarities of the first voltage and the second voltage are opposite to that of the signal. Thus, the charge placement in the storing material could be precisely controlled within a small range of charge state and produce a multi-bits/cell of higher digital storage density.

Abstract: A non-volatile memory having a control gate (14) and a sidewall select gate (28) is illustrated. The sidewall select gate (28) is formed in conjunction with a semiconductor doped oxide (20) to form a non-volatile memory cell (7). The semiconductor element used to dope the oxide layer (20) will generally include silicon or germanium. The non-volatile memory cell (7) is programmed by storing electrons in the doped oxide (20), and is erased using band-to-band tunneling.