Patents by Inventor Leel S. Janzen
Leel S. Janzen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8677170Abstract: An apparatus for generating a delayed clock signal. The apparatus is a computer system with a processor to which a memory device is coupled. The memory device has a delay clock generator that has a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.Type: GrantFiled: February 24, 2012Date of Patent: March 18, 2014Assignee: Round Rock Research, LLCInventor: Leel S. Janzen
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Publication number: 20120159229Abstract: An apparatus for generating a delayed clock signal. The apparatus is a computer system with a processor to which a memory device is coupled. The memory device has a delay clock generator that has a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.Type: ApplicationFiled: February 24, 2012Publication date: June 21, 2012Applicant: ROUND ROCK RESEARCH, LLC.Inventor: Leel S. Janzen
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Patent number: 8127171Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.Type: GrantFiled: September 28, 2009Date of Patent: February 28, 2012Assignee: Round Rock Research, LLCInventor: Leel S. Janzen
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Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages
Patent number: 8037237Abstract: A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The method includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.Type: GrantFiled: June 22, 2010Date of Patent: October 11, 2011Assignee: Round Rock Research, LLCInventor: Leel S. Janzen -
METHOD AND CIRCUIT FOR ADJUSTING A SELF-REFRESH RATE TO MAINTAIN DYNAMIC DATA AT LOW SUPPLY VOLTAGES
Publication number: 20100262769Abstract: A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The method includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.Type: ApplicationFiled: June 22, 2010Publication date: October 14, 2010Applicant: ROUND ROCK RESEARCH, LLCInventor: Leel S. Janzen -
Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages
Patent number: 7747815Abstract: A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The method includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.Type: GrantFiled: October 20, 2005Date of Patent: June 29, 2010Assignee: Round Rock Research, LLCInventor: Leel S. Janzen -
Publication number: 20100023793Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.Type: ApplicationFiled: September 28, 2009Publication date: January 28, 2010Inventor: Leel S. Janzen
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Patent number: 7610502Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.Type: GrantFiled: July 25, 2006Date of Patent: October 27, 2009Assignee: Micron Technology, Inc.Inventor: Leel S. Janzen
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Patent number: 7610503Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.Type: GrantFiled: July 25, 2006Date of Patent: October 27, 2009Assignee: Micron Technology, Inc.Inventor: Leel S. Janzen
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Patent number: 7511531Abstract: A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up transistor. The supplemental pull-up circuit is configured to generate a supplemental pull-up output signal with the first pull-up output signal and the supplemental pull-up output signal, forming a pull-up output signal. The output buffer further includes a pull-down circuit, including a first pull-down transistor for providing a first pull-down output signal and a supplemental pull-down circuit in parallel with the first pull-down transistor. The supplemental pull-down circuit is configured to generate a supplemental pull-down output signal with the pull-up output signal and the pull-down output signal coupled to form an output buffer output signal.Type: GrantFiled: September 11, 2006Date of Patent: March 31, 2009Assignee: Micron Technology, Inc.Inventors: Dong Pan, Leel S. Janzen
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Patent number: 7350093Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.Type: GrantFiled: July 25, 2006Date of Patent: March 25, 2008Assignee: Micron Technology, Inc.Inventor: Leel S. Janzen
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Patent number: 7308594Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.Type: GrantFiled: July 25, 2006Date of Patent: December 11, 2007Assignee: Micron Technology, Inc.Inventor: Leel S. Janzen
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Patent number: 7278045Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.Type: GrantFiled: July 25, 2006Date of Patent: October 2, 2007Assignee: Micron Technology, Inc.Inventor: Leel S. Janzen
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Patent number: 7275172Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.Type: GrantFiled: January 11, 2006Date of Patent: September 25, 2007Assignee: Micron Technology, Inc.Inventor: Leel S. Janzen
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Patent number: 7116129Abstract: A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up transistor. The supplemental pull-up circuit is configured to generate a supplemental pull-up output signal with the first pull-up output signal and the supplemental pull-up output signal forming a pull-up output signal. The output buffer further includes a pull-down circuit, including a first pull-down transistor for providing a first pull-down output signal and a supplemental pull-down circuit in parallel with the first pull-down transistor. The supplemental pull-down circuit is configured to generate a supplemental pull-down output signal with the pull-up output signal and the pull-down output signal coupled to form an output buffer output signal.Type: GrantFiled: July 20, 2004Date of Patent: October 3, 2006Assignee: Micron Technology, Inc.Inventors: Dong Pan, Leel S. Janzen
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Patent number: 7065666Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.Type: GrantFiled: November 13, 2003Date of Patent: June 20, 2006Assignee: Micron Technology, Inc.Inventor: Leel S. Janzen
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Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages
Patent number: 7013363Abstract: A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The method includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.Type: GrantFiled: October 14, 2003Date of Patent: March 14, 2006Assignee: Micron Technology, Inc.Inventor: Leel S. Janzen -
Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages
Publication number: 20040153603Abstract: A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The method includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.Type: ApplicationFiled: October 14, 2003Publication date: August 5, 2004Inventor: Leel S. Janzen -
Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages
Patent number: 6646942Abstract: A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The method includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.Type: GrantFiled: October 9, 2001Date of Patent: November 11, 2003Assignee: Micron Technology, Inc.Inventor: Leel S. Janzen -
Patent number: 6603697Abstract: A circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The circuit includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.Type: GrantFiled: July 31, 2002Date of Patent: August 5, 2003Assignee: Micron Technology, Inc.Inventor: Leel S. Janzen