Abstract: A system to generate true random numbers includes a RAM array, a null-read controller and a hash generator. The RAM array has memory cells and a sense amplifier. The memory cells store data therein, the cells are connected in rows to word lines and in columns to pairs of bit lines, and the sense amplifier senses a differential input signal. The null-read controller implements a null-read operation by the sense amplifier of a portion of the RAM array. The hash generator receives a null-read result from the null-read operation and outputs a partial true random number based on the null-read result.

Abstract: A memory array may include a read bit line (RBL), a complimentary read bit line (RBLb), a plurality of storage cells each selectably coupled to the RBL and the RBLb such that an XNOR of a read enable (RE) signal and a content of the respective storage cell is output to the RBL in response to the RE signal and an XOR of the RE signal and the content of the respective storage cell is output to the RBLb in response to the RE signal, and a sensing circuit coupled to the RBL and the RBLb and configured to compare a signal on the RBL to a signal on the RBLb and output a comparison result.

Abstract: A system and method for single cycle binary matrix multiplication in neural network computations is disclosed. The system includes a memory array storing binary weights, an input unit for activating rows based on a binary activation vector, and per-column majority sense amplifiers. The system performs binary matrix multiplication in a single cycle, enabling efficient implementation of binary neural networks. The memory array may include sections for weights and inverse weights, with corresponding activation register sections. Differential sense amplifiers may implement the majority function. The system can be applied to convolutional neural networks, using SRAM arrays for image storage and processing. Methods for determining majority votes and counting activated bits using iterative modification of the activation vector are also described.

Abstract: A semiconductor package assembly includes an interposer mounted on a package substrate, a column parallel processor mounted on and electrically connected to the interposer, and a high bandwidth memory (HBM) stack mounted on the parallel processor. The parallel processor includes a memory array with rows and columns, with operations occurring in the columns. Columns of the HBM stack are electrically connected to the columns of the parallel processor. The column parallel processor includes an associative processing unit (APU), a switch fabric for managing data routing, a local SRAM for temporary storage, and a buffer for managing data flow between the HBM stack and processing elements. The assembly is configured to process large language models and perform pattern searches within large datasets stored in the HBM stack.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Abstract: A system to generate true random numbers includes a RAM array, a null-read controller and a hash generator. The RAM array has memory cells and a sense amplifier. The memory cells store data therein, the cells are connected in rows to word lines and in columns to pairs of bit lines, and the sense amplifier senses a differential input signal. The null-read controller implements a null-read operation by the sense amplifier of a portion of the RAM array.

Abstract: A storage array for computational memory cells formed as a memory/processing array provides storage of the data without using the more complicated computational memory cells for storage. The storage array may have multiple columns of the storage cells coupled to a column of the computational memory cells. The storage array may have ECC circuitry.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Abstract: An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.