Patents by Inventor Leena K. Puthiyedath

Leena K. Puthiyedath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10802984
    Abstract: Examples may include techniques for persistent memory virtualization. Persistent memory maintained at one or more memory devices coupled with a host computing device may be allocated and assigned to a virtual machine (VM) hosted by the host computing device. The allocated persistent memory based on a file based virtual memory to be used by the VM. An extended page table (EPT) may be generated to map physical memory pages of the one or more memory devices to virtual logical blocks of the file based virtual memory. Elements of the VM then enumerate a presence of the assigned allocated persistent memory, create a virtual disk abstraction for the file based virtual memory and use the EPT to directly access the assigned allocated persistent memory.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Vivekananthan Sanjeepan, Leena K. Puthiyedath, Chandan Apsangi, Nikhil Talpallikar, Abinash K. Barik
  • Patent number: 10725920
    Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
    Type: Grant
    Filed: April 8, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Herbert H. Hum, Brinda Ganesh, James R. Vash, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger, Eric J. Dehaemer, Adrian C. Moga, Michelle M. Sebot, Richard L. Carlson, David Bubien, Eric Delano
  • Patent number: 10725919
    Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
    Type: Grant
    Filed: April 8, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Herbert H. Hum, Brinda Ganesh, James R. Vash, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger, Eric J. Dehaemer, Adrian C. Moga, Michelle M. Sebot, Richard L. Carlson, David Bubien, Eric Delano
  • Patent number: 10705960
    Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
    Type: Grant
    Filed: April 8, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Herbert H. Hum, Brinda Ganesh, James R. Vash, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger, Eric J. Dehaemer, Adrian C. Moga, Michelle M. Sebot, Richard L. Carlson, David Bubien, Eric DeLano
  • Patent number: 10657068
    Abstract: Examples may include techniques for an all persistent memory file system. The techniques to include allocating physical memory pages of memory devices of a persistent memory platform coupled with a computing platform. The techniques to also include storing context or relocated files to persistent memory physical address spaces for the memory devices and mapping process virtual address spaces for a working set associated with one or more instantiations of a program by circuitry at the computing platform.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventor: Leena K. Puthiyedath
  • Patent number: 10564986
    Abstract: A disclosed example method to suspend and resume a device includes: after detecting a low-power suspend mode request, determining a storage performance of the device to store suspend state data; based on the storage performance of the device, setting a suspend flag to indicate a low-power suspend mode to a processor platform; when resuming from the low-power suspend mode, confirming a setting of a resume flag from the processor platform, the resume flag to notify an operating system to resume from the low-power suspend mode; and when the resume flag is set, restoring state data corresponding to an operating system context from a non-volatile dual-purpose system and storage memory.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventors: Michael A. Rothman, Vincent J. Zimmer, Glenn J. Hinton, Barnes Cooper, Leena K. Puthiyedath
  • Publication number: 20190258502
    Abstract: Examples may include techniques for persistent memory virtualization. Persistent memory maintained at one or more memory devices coupled with a host computing device may be allocated and assigned to a virtual machine (VM) hosted by the host computing device. The allocated persistent memory based on a file based virtual memory to be used by the VM. An extended page table (EPT) may be generated to map physical memory pages of the one or more memory devices to virtual logical blocks of the file based virtual memory. Elements of the VM then enumerate a presence of the assigned allocated persistent memory, create a virtual disk abstraction for the file based virtual memory and use the EPT to directly access the assigned allocated persistent memory.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 22, 2019
    Inventors: Vivekananthan SANJEEPAN, Leena K. PUTHIYEDATH, Chandan APSANGI, Nikhil TALPALLIKAR, Abinash K. BARIK
  • Patent number: 10210012
    Abstract: Examples may include techniques for persistent memory virtualization. Persistent memory maintained at one or more memory devices coupled with a host computing device may be allocated and assigned to a virtual machine (VM) hosted by the host computing device. The allocated persistent memory based on a file based virtual memory to be used by the VM. An extended page table (EPT) may be generated to map physical memory pages of the one or more memory devices to virtual logical blocks of the file based virtual memory. Elements of the VM then enumerate a presence of the assigned allocated persistent memory, create a virtual disk abstraction for the file based virtual memory and use the EPT to directly access the assigned allocated persistent memory.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventors: Vivekananthan Sanjeepan, Leena K. Puthiyedath, Chandan Apsangi, Nikhil Talpallikar, Abinash K. Barik
  • Publication number: 20190050344
    Abstract: Examples may include techniques for an all persistent memory file system. The techniques to include allocating physical memory pages of memory devices of a persistent memory platform coupled with a computing platform. The techniques to also include storing context or relocated files to persistent memory physical address spaces for the memory devices and mapping process virtual address spaces for a working set associated with one or more instantiations of a program by circuitry at the computing platform.
    Type: Application
    Filed: March 22, 2018
    Publication date: February 14, 2019
    Inventor: Leena K. PUTHIYEDATH
  • Patent number: 10073779
    Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Herbert H. Hum, Brinda Ganesh, James R. Vash, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger, Eric J. Dehaemer, Adrian C. Moga, Michelle M. Sebot, Richard L. Carlson, David Bubien, Eric Delano
  • Publication number: 20180225213
    Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
    Type: Application
    Filed: April 8, 2018
    Publication date: August 9, 2018
    Inventors: Herbert H. HUM, Brinda GANESH, James R. VASH, Ganesh KUMAR, Leena K. PUTHIYEDATH, Scott J. ERLANGER, Eric J. DEHAEMER, Adrian C. MOGA, Michelle M. SEBOT, Richard L. CARLSON, David BUBIEN, Eric DELANO
  • Publication number: 20180225212
    Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
    Type: Application
    Filed: April 8, 2018
    Publication date: August 9, 2018
    Inventors: Herbert H. HUM, Brinda GANESH, James R. VASH, Ganesh KUMAR, Leena K. PUTHIYEDATH, Scott J. ERLANGER, Eric J. DEHAEMER, Adrian C. MOGA, Michelle M. SEBOT, Richard L. CARLSON, David BUBIEN, Eric DELANO
  • Publication number: 20180225211
    Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.
    Type: Application
    Filed: April 8, 2018
    Publication date: August 9, 2018
    Inventors: Herbert H. HUM, Brinda GANESH, James R. VASH, Ganesh KUMAR, Leena K. PUTHIYEDATH, Scott J. ERLANGER, Eric J. DEHAEMER, Adrian C. MOGA, Michelle M. SEBOT, Richard L. CARLSON, David Bubien, Eric Delano
  • Publication number: 20180181411
    Abstract: A disclosed example method to suspend and resume a device includes: after detecting a low-power suspend mode request, determining a storage performance of the device to store suspend state data; based on the storage performance of the device, setting a suspend flag to indicate a low-power suspend mode to a processor platform; when resuming from the low-power suspend mode, confirming a setting of a resume flag from the processor platform, the resume flag to notify an operating system to resume from the low-power suspend mode; and when the resume flag is set, restoring state data corresponding to an operating system context from a non-volatile dual-purpose system and storage memory.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Michael A. Rothman, Vincent J. Zimmer, Glenn J. Hinton, Barnes Cooper, Leena K. Puthiyedath
  • Patent number: 10001953
    Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 19, 2018
    Assignee: Intel Corporation
    Inventors: Leena K. Puthiyedath, Blaise Fanning, Toby Opferman, James B. Crossland
  • Patent number: 9958926
    Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to provide instant responses to sleep state transitions. The computer system includes a processor coupled to an NVRAM, which is accessible by the processor without passing through an I/O subsystem. The NVRAM is byte-rewritable and byte-erasable by the processor. In response to a request to enter a powered sleep state, the computer system converts the powered sleep state into a powered-off sleep state with system memory context stored in the NVRAM. The powered sleep state is defined as a state in which power is supplied to volatile random access memory in the computer system, and the powered-off sleep state is defined as a state in which power is removed from the volatile random access memory. In response to a wake event, the computer system resumes working state operations using the system memory context stored in the NVRAM.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: May 1, 2018
    Assignee: Intel Corporation
    Inventors: Leena K. Puthiyedath, Raj K. Ramanujan, Michael Rothman, Blaise Fanning, Vincent J. Zimmer
  • Publication number: 20180004649
    Abstract: Examples may include techniques to format a persistent memory file. Memory representations of data structures maintained in virtual addresses of a process virtual memory space for a computing device may be received. A file may be formatted to store or map the receive memory representations of the data structures to a persistent memory maintained at one or more memory devices coupled with the computing device. The file format to require no serialization or marshalling transformations to write or map memory representations of the data structures to the persistent memory.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Applicant: Intel Corporation
    Inventor: Leena K. Puthiyedath
  • Publication number: 20170371695
    Abstract: Examples may include techniques for persistent memory virtualization. Persistent memory maintained at one or more memory devices coupled with a host computing device may be allocated and assigned to a virtual machine (VM) hosted by the host computing device. The allocated persistent memory based on a file based virtual memory to be used by the VM. An extended page table (EPT) may be generated to map physical memory pages of the one or more memory devices to virtual logical blocks of the file based virtual memory. Elements of the VM then enumerate a presence of the assigned allocated persistent memory, create a virtual disk abstraction for the file based virtual memory and use the EPT to directly access the assigned allocated persistent memory.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 28, 2017
    Applicant: Intel Corporation
    Inventors: Vivekananthan Sanjeepan, Leena K. Puthiyedath, Chandan Apsangi, Nikhil Talpallikar, Abinash K. Barik
  • Publication number: 20170249008
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for initiating a transition into a lower power state, determining that a device process prevents a platform processing device from completing the transition to the lower power state and interrupting a processing component from an intermediate power state in order to process the process prior to execution of a defined event.
    Type: Application
    Filed: October 3, 2016
    Publication date: August 31, 2017
    Applicant: INTEL CORPORATION
    Inventors: LEENA K. PUTHIYEDATH, ANIL AGGARWAL, QINGDA LU, RAHUL SETH, MICHAEL C. WALZ
  • Publication number: 20170139649
    Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.
    Type: Application
    Filed: December 15, 2016
    Publication date: May 18, 2017
    Inventors: Leena K. PUTHIYEDATH, Blaise FANNING, Tony OPFERMAN, James B. CROSSLAND