Patents by Inventor Leena Paivikki Buchwalter

Leena Paivikki Buchwalter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8314500
    Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: November 20, 2012
    Assignee: Ultratech, Inc.
    Inventors: Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Jonathan H. Griffith, Donald W. Henderson, Sung Kwon Kang, Eric H. Laine, Christian Lavoie, Paul A. Lauro, Valérie Anne Oberson, Da-Yuan Shih, Kamalesh K Srivastava, Michael J. Sullivan
  • Publication number: 20120270351
    Abstract: A method of removal of a first and second sacrificial layer wherein an O2 plasma or an O2-containing environment is introduced to a cavity and a gap region through a plurality of via holes in a cavity capping material.
    Type: Application
    Filed: July 2, 2012
    Publication date: October 25, 2012
    Applicant: International Business Machines Corporation
    Inventors: Leena Paivikki BUCHWALTER, Kevin Kok CHAN, Timothy Joseph DALTON, Christopher Vincent JAHNES, Jennifer Louise LUND, Kevin Shawn PETRARCA, James Louis SPEIDELL, James Francis ZIEGLER
  • Patent number: 8269291
    Abstract: A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Leena Paivikki Buchwalter, Kevin Kok Chan, Timothy Joseph Dalton, Christopher Vincent Jahnes, Jennifer Louise Lund, Kevin Shawn Petraraca, James Louis Speidell, James Francis Ziegler
  • Patent number: 8187923
    Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: May 29, 2012
    Assignee: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Leena Paivikki Buchwalter, Matthew J. Farinelli, Sherif A. Goma, Raymond R. Horton, Edmund J. Sprogis
  • Patent number: 7943412
    Abstract: A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: May 17, 2011
    Assignee: International Business Machines Corporation
    Inventors: Leena Paivikki Buchwalter, Kevin Kok Chan, Timothy Joseph Dalton, Christopher Vincent Jahnes, Jennifer Louise Lund, Kevin Shawn Petrarca, James Louis Speidell, James Francis Ziegler
  • Publication number: 20110109405
    Abstract: A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane.
    Type: Application
    Filed: January 14, 2011
    Publication date: May 12, 2011
    Applicant: International Business Machines Corporation
    Inventors: Leena Paivikki Buchwalter, Kevin Kok Chan, Timothy Joseph Dalton, Christopher Vincent Jahnes, Jennifer Louise Lund, Kevin Shawn Petrarca, James Louis Speidell, James Francis Ziegler
  • Patent number: 7932169
    Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: April 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Jonathan H. Griffith, Donald W. Henderson, Sung Kwon Kang, Eric H. Laine, Christian Lavoie, Paul A. Lauro, Valérie Anne Oberson, Da-Yuan Shih, Kamalesh K Srivastava, Michael J. Sullivan
  • Patent number: 7815968
    Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gareth Hougham, Leena Paivikki Buchwalter, Stephen L. Buchwalter, Jon Casey, Claudius Feger, Matteo Flotta, Jeffrey D. Gelmore, Kathleen C. Hinge, Anurag Jain, Sung K. Kang, John U. Knickerbocker
  • Publication number: 20100062597
    Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
    Type: Application
    Filed: October 5, 2009
    Publication date: March 11, 2010
    Inventors: Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Jonathan H. Griffith, Donald W. Henderson, Sung Kwon Kang, Eric H. Laine, Christian Lavoie, Paul A. Lauro, Valérie Anne Oberson, Da-Yuan Shih, Kamalesh K. Srivastava, Michael J. Sullivan
  • Patent number: 7615405
    Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: November 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Leena Paivikki Buchwalter, Raymond R. Horton, John Ulrich Knickerbocker, Cornelia K. Tsang, Steven Lorenz Wright
  • Publication number: 20090108381
    Abstract: A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material.
    Type: Application
    Filed: December 10, 2002
    Publication date: April 30, 2009
    Applicant: International Business Machines Corporation
    Inventors: Leena Paivikki Buchwalter, Kevin Kok Chan, Timothy Joseph Dalton, Christopher Vincent Jahnes, Jennifer Louise Lund, Kevin Shawn Petrarca, James Louis Speidell, James Francis Ziegler
  • Patent number: 7456046
    Abstract: A method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semiconductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips and selectively, other devices in the technology.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: November 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Leena Paivikki Buchwalter, Russell A. Budd, Chirag S. Patel
  • Patent number: 7452568
    Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Gareth Hougham, Leena Paivikki Buchwalter, Stephen L. Buchwalter, Jon Casey, Claudius Feger, Matteo Flotta, Jeffrey D. Gelorme, Kathleen C. Hinge, Anurag Jain, Sung K. Kang, John U. Knickerbocker
  • Publication number: 20080217778
    Abstract: A method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semiconductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips and selectively, other devices in the technology.
    Type: Application
    Filed: May 13, 2008
    Publication date: September 11, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leena Paivikki Buchwalter, Russell A. Budd, Chirag S. Patel
  • Publication number: 20080182362
    Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.
    Type: Application
    Filed: October 15, 2007
    Publication date: July 31, 2008
    Inventors: Paul Stephen Andry, Leena Paivikki Buchwalter, Raymond R. Horton, John Ulrich Knickerbocker, Cornelia K. Tsang, Steven Lorenz Wright
  • Publication number: 20080157395
    Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Jonathan H. Griffith, Donald W. Henderson, Sung Kwon Kang, Eric H. Laine, Christian Lavoie, Paul A. Lauro, Valerie Anne Oberson, Da-Yuan Shih, Kamalesh K. Srivastava, Michael J. Sullivan
  • Patent number: 7282391
    Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: October 16, 2007
    Assignee: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Leena Paivikki Buchwalter, Raymond R. Horton, John Ulrich Knickerbocker, Cornelia K. Tsang, Steven Lorenz Wright
  • Patent number: 7276787
    Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: October 2, 2007
    Assignee: International Business Machines Corporation
    Inventors: Daniel Charles Edelstein, Paul Stephen Andry, Leena Paivikki Buchwalter, Jon Alfred Casey, Sherif A. Goma, Raymond R. Horton, Gareth Geoffrey Hougham, Michael Wayne Lane, Xiao Hu Liu, Chirag Suryakant Patel, Edmund Juris Sprogis, Michelle Leigh Steen, Brian Richard Sundlof, Cornelia K. Tsang, George Frederick Walker
  • Patent number: 7019402
    Abstract: This disclosure teaches a method of filling deep vias or capping deep conducting paste filled vias in silicon or glass substrate using laser assisted chemical vapor deposition of metals. This method uses a continuous wave or pulsed laser to heat the via bottom and the growing metal fill selectively by selecting the laser wavelength such that silicon and/or glass do not absorb the energy of the laser in any appreciable manner to cause deposition in the field. Alternatively holographic mask or an array of micro lenses may be used to focus the laser beams to the vias to fill them with metal. The substrate is moved in a controlled manner in the z-direction away from the laser at about the rate of deposition thus causing the laser heating to be focused on the surface region of the growing metal fill.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: March 28, 2006
    Assignee: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Leena Paivikki Buchwalter, Russell Alan Budd, Thomas Anthony Wassick
  • Patent number: 6818843
    Abstract: Microswitch, comprising a base element (G) with a contact surface (KG) and an electrode (EG), and a switching element (S) with a contact surface (KS) and an electrode (ES) disposed opposite the electrode (EG) of the base element (G) at a distance (g). The switching element (S) is provided with a spring constant and is connected at least with a part of its edge portion with the base element (G) in a fixed manner. The contact surfaces (KG, KS) form a switching contact which is closable against a reaction force caused by the spring constant by means of a voltage applied to the electrodes (EG, ES). The base element (G) and the switching element (S) each comprise an auxiliary electrode (HG, HS) at a distance (a) from the electrode (EG, ES), to which a voltage can be applied. For opening the switching contact the electrodes (EG, ES) have a first voltage potential (U1) and the auxiliary electrodes have a second voltage potential (U2) of the voltage.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: November 16, 2004
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventors: Michael Meixner, Leena Paivikki Buchwalter, Jennifer Louise Lund, Hariklia Deligianni