Patents by Inventor Leena Puthiyedath

Leena Puthiyedath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11630687
    Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: April 18, 2023
    Assignee: Tahoe Research, Ltd.
    Inventors: Atul Khare, Leena Puthiyedath, Asit Mallick, Jim Coke, Michael Mishaeli, Gilbert Neiger, Vivekananthan Sanjeepan, Jason Brandt
  • Patent number: 11023382
    Abstract: Implementations of using tiles for caching are detailed In some implementations, an instruction execution circuitry executes one or more instructions, a register state cache coupled to the instruction execution circuitry holds thread register state in a plurality of registers, and backing storage pointer storage stores a backing storage pointer, wherein the backing storage pointer is to reference a state backing storage area in external memory to store the thread register state stored in the register state cache.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Raanan Sade, Jason Brandt, Mark J. Charney, Joseph Nuzman, Leena Puthiyedath, Rinat Rappoport, Vivekananthan Sanjeepan, Robert Valentine
  • Publication number: 20190042448
    Abstract: Implementations of using tiles for caching are detailed In some implementations, an instruction execution circuitry executes one or more instructions, a register state cache coupled to the instruction execution circuitry holds thread register state in a plurality of registers, and backing storage pointer storage stores a backing storage pointer, wherein the backing storage pointer is to reference a state backing storage area in external memory to store the thread register state stored in the register state cache.
    Type: Application
    Filed: December 22, 2017
    Publication date: February 7, 2019
    Inventors: Raanan SADE, Jason BRANDT, Mark J. CHARNEY, Joseph NUZMAN, Leena PUTHIYEDATH, Rinat RAPPOPORT, Vivekananthan SANJEEPAN, Robert VALENTINE
  • Publication number: 20180276027
    Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.
    Type: Application
    Filed: February 20, 2018
    Publication date: September 27, 2018
    Inventors: Atul KHARE, Leena PUTHIYEDATH, Asit MALLICK, Jim COKE, Michael MISHAELI, Gilbert NEIGER, Vivekananthan SANJEEPAN, Jason BRANDT
  • Patent number: 9898330
    Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventors: Atul Khare, Leena Puthiyedath, Asit Mallick, Jim Coke, Michael Mishaeli, Gilbert Neiger, Vivekananthan Sanjeepan, Jason Brandt
  • Publication number: 20150135195
    Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.
    Type: Application
    Filed: November 11, 2013
    Publication date: May 14, 2015
    Inventors: Atul KHARE, Leena PUTHIYEDATH, Asit MALLICK, Jim COKE, Michael MISHAELI, Gilbert NEIGER, Vivekananthan SANJEEPAN, Jason BRANDT
  • Publication number: 20060288391
    Abstract: A method and system of analyzing the perceived quality of streaming media that includes transmitting at least one data packet from a stream sender to a stream receiver via a network connection; analyzing the data packets at the stream receiver, where the stream receiver determines whether there are data packets missing from the stream sender's data packets; requesting retransmission of specific data packets missing from the stream receiver; and retransmitting at least one specific data packet missing from the stream sender to the stream receiver.
    Type: Application
    Filed: August 23, 2006
    Publication date: December 21, 2006
    Applicant: Intel Corporation
    Inventor: Leena Puthiyedath