Abstract: An integrated circuit in dynamic MOS logic is composed of combinatory and sequential logic elements. Each of the latter comprises a succession of an input gate, an intermediate gate and an output gate which are activated to conduct by a corresponding phase of the first one and subsequent phases of a clock pulse cycle. The combinatory logic elements are all composed of gates of a single type, while the input signals are applied via the sequential logic elements and the output signals are output again via the latter elements. Thus, in the combinatory network only a sole type of interference is still relevant.

Abstract: A word-organized, content-addressable memory comprises per word location a validity indicator, having a position "valid" and a position "invalid", and a correspondence indicator. The following functions can be performed:(a) associative searching and reading of the content of a word for which correspondence occurs (R);(b) reading the next word in sequence of words for which correspondence occurs (SR);(c) loading a mask word in the mask register (LM);(d) selective invalidating of the content of one or more predetermined word locations (CPM);(e) writing in an empty word location, i.e. a location not having a valid data content (WFP);(f) writing data in a number of selective bit positions of one or more words for which correspondence occurs (WP).There is also provided a mask register whose data activate the comparisons as well as the outputting of data for which no comparison has taken place.As a result of such an organization, a very versatile use is realized for a comparatively inexpensive memory.