Abstract: A method and apparatus for multi-task processing are disclosed. The method includes obtaining a base output corresponding to a first layer, restoring an input map corresponding to a second layer, obtaining an output map corresponding to the second layer, obtaining a delta output map corresponding to the second layer, and storing the base output map and the delta output map.

Abstract: A processor-implemented method with multi-task processing includes: obtaining weights of a first neural network; obtaining first delta weights of a second neural network that is fine-tuned from the first neural network, based on a target task; performing an operation of the second neural network on first input data, based on sums of the weights of the first neural network and the first delta weights; obtaining second delta weights of a third neural network that is fine-tuned from the first neural network, based on a change of the target task; replacing the first delta weights with the second delta weights; and performing an operation of the third neural network on second input data, based on sums of the weights of the first neural network and the second delta weights, wherein the first delta weights comprise difference values in the weights of the first neural network and weights of the second neural network, and the second delta weight comprises difference values in the weights of the first neural network an

Abstract: A method with neural network compression includes: generating a second neural network by fine-tuning a first neural network, which is pre-trained based on training data, for a predetermined purpose; determining delta weights corresponding to differences between weights of the first neural network and weights of the second neural network; compressing the delta weights; retraining the second neural network updated based on the compressed delta weights and the weights of the first neural network; and encoding and storing the delta weights updated by the retraining of the second neural network.

Abstract: An encoding method includes receiving input data represented by a 16-bit half floating point, adjusting a number of bits of an exponent and a mantissa of the input data to split the input data into 4-bit units, and encoding the input data in which the number of bits has been adjusted such that the exponent is a multiple of “4”.

Abstract: A neural network data quantizing method includes: obtaining local quantization data by firstly quantizing, based on a local maximum value for each output channel of a current layer of a neural network, global recovery data obtained by recovering output data of an operation of the current layer based on a global maximum value corresponding to a previous layer of the neural network; storing the local quantization data in a memory to perform an operation of a next layer of the neural network; obtaining global quantization data by secondarily quantizing, based on a global maximum value corresponding to the current layer, local recovery data obtained by recovering the local quantization data based on the local maximum value for each output channel of the current layer; and providing the global quantization data as input data for the operation of the next layer.

Abstract: A memory controller includes a scheduler that decides a processing order of a plurality of requests provided from an external device with reference to a timing parameter value for each of the requests; and a timing control circuit that adjusts the timing parameter value according to a corresponding address to access a memory device, the corresponding address being used to process a corresponding request of the plurality of requests.

Abstract: A memory controller schedules requests to memory devices according to scores. For this purpose, the memory controller variably adjusts weights for determining the scores with respect to the requests, calculates the scores using the weights, and determines a processing order of the requests according to the scores. The memory controller includes a request queue, a scheduler, and a weight generation circuit. The request queue stores the requests provided from an external device. The scheduler calculates a score for each request included in the request queue and determines the processing order of the requests based on the scores for the requests. The weight generation circuit generates a weight vector including the weights used to calculate the scores.

Abstract: A memory controller includes a request queue that stores requests provided from an external device, a scheduler that calculates a score for each request included in the request queue and determines a processing order of the requests based on the scores for the requests, and a weight generation circuit that generates a weight vector including weights used to calculated the scores.

Abstract: A memory controller includes a scheduler that decides a processing order of a plurality of requests provided from an external device with reference to a timing parameter value for each of the requests; and a timing control circuit that adjusts the timing parameter value according to a corresponding address to access a memory device, the corresponding address being used to process a corresponding request of the plurality of requests.

Abstract: A data signal receiver includes a clock signal filter, a falling pulse signal generator, a mixing block, and a sampler. The clock signal filter generates a first filtered clock signal and a second filtered clock signal by filtering a clock signal. The falling pulse signal generator generates a falling pulse signal based on the first filtered clock signal. The mixing block generates a mixed data signal by mixing a data signal and the falling pulse signal. The sampler generates a recovered data signal by sampling the mixed data signal in response to the second filtered clock signal.

Abstract: A data signal receiver includes a clock signal filter, a falling pulse signal generator, a mixing block, and a sampler. The clock signal filter generates a first filtered clock signal and a second filtered clock signal by filtering a clock signal. The falling pulse signal generator generates a falling pulse signal based on the first filtered clock signal. The mixing block generates a mixed data signal by mixing a data signal and the falling pulse signal. The sampler generates a recovered data signal by sampling the mixed data signal in response to the second filtered clock signal.

Abstract: A graphic processor includes a rasterizer configured to process vertex data to generate fragment data based on a maximum depth value, a minimum depth value, and a mask bit of each pixel included in one tile, each mask bit indicating whether each pixel is drawn or not, the vertex data including three dimensional information of the pixels, a pixel shader configured to process the fragment data to generate color data, and a raster operation unit configured to convert the color data to pixel data to be displayed.

Abstract: A graphic processor includes a rasterizer configured to process vertex data to generate fragment data based on a maximum depth value, a minimum depth value, and a mask bit of each pixel included in one tile, each mask bit indicating whether each pixel is drawn or not, the vertex data including three dimensional information of the pixels, a pixel shader configured to process the fragment data to generate color data, and a raster operation unit configured to convert the color data to pixel data to be displayed.

Abstract: A multi-phase signal generator may include a duty control buffer configured to receive a first differential input signal and a second differential input signal, and generate a first differential output signal and a second differential output signal having variable duty ratios based on a control voltage, a first edge combiner configured to generate a first pulse signal based on first edges of the respective first and second differential output signals, a second edge combiner configured to generate a second pulse signal based on second edges of the respective first and second differential output signals, and a control voltage generator configured to generate the control voltage in response to a logic signal obtained by performing a logic operation on the first and second pulse signals.

Abstract: A multi-phase signal generator may include a duty control buffer configured to receive a first differential input signal and a second differential input signal, and generate a first differential output signal and a second differential output signal having variable duty ratios based on a control voltage, a first edge combiner configured to generate a first pulse signal based on first edges of the respective first and second differential output signals, a second edge combiner configured to generate a second pulse signal based on second edges of the respective first and second differential output signals, and a control voltage generator configured to generate the control voltage in response to a logic signal obtained by performing a logic operation on the first and second pulse signals.

Abstract: Provided are a 3D graphics rendering engine for processing fragments and a 3D graphics rendering engine method. The 3D graphics rendering engine positions a depth filter having a specific z value in a depth filtering circuit and compares a depth value of each of a plurality of fragments forming a first object being rasterized in a 3D space with a depth value of the depth filter. Then, the 3D graphics rendering engine stores data, which is mapped to the depth filter and corresponds to each of the fragments of the first object, in a storage device, based on the result of the comparison concerning the first object and rasterizes each of a plurality of fragments forming a second object.

Abstract: An anisotropic texture filtering method using area coverage weight of sub-texel precision includes the steps of executing filtering by applying weights to texels; representing four sides of the footprint by four linear equations for computing area coverage weight; obtaining sub-texel masks from a table by addresses given by values of line equations; and calculating the final area coverage weight with four sub-texel masks obtained in the previous step.

Abstract: Provided are a 3D graphics rendering engine for processing fragments and a 3D graphics rendering engine method. The 3D graphics rendering engine positions a depth filter having a specific z value in a depth filtering circuit and compares a depth value of each of a plurality of fragments forming a first object being rasterized in a 3D space with a depth value of the depth filter. Then, the 3D graphics rendering engine stores data, which is mapped to the depth filter and corresponds to each of the fragments of the first object, in a storage device, based on the result of the comparison concerning the first object and rasterizes each of a plurality of fragments forming a second object.

Abstract: An image scaling method and apparatus converting an input image into an aimed image with suitable resolution for application, in the case that the input image and the aimed image are different in resolution, using continuous domain filtering and interpolation method. The invention utilizes domain filter of regular square type and generates filter coefficient based on area occupancy ratio of filter window according to the area of corresponding pixel extending the applied filter window and then obtains scaled image through the method of computing weighted average value, which is determined through multiplication of the generated filter coefficient and value of each pixel. By using image scaling method of the invention, there is an advantage of much lower cost in hardware implementation of an image scaler in comparison with conventional image scaling methods.

Abstract: The present invention relates to a method and apparatus of anisotropic texture filtering to obtain high quality image for three-dimensional graphics by using area coverage weight of sub-texel precision.