Patents by Inventor Leibing Yuan

Leibing Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8927386
    Abstract: The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: January 6, 2015
    Assignees: CSMC Technologies FAB1 Co., Ltd., CSMC Technologies FAB2 Co., Ltd.
    Inventors: Tzong Shiann Wu, Genyi Wang, Leibing Yuan, Pengpeng Wu
  • Publication number: 20130196489
    Abstract: The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.
    Type: Application
    Filed: May 31, 2012
    Publication date: August 1, 2013
    Inventors: Tzong Shiann Wu, Genyi Wang, Leibing Yuan, Pengpeng Wu