Abstract: An apparatus that includes a set of memory components of a memory sub-system is disclosed for selectively adjusting a touch up program pulse of an SG. The memory sub-system includes a processing device that detects a condition for performing a select gate (SG) scan for a set of SGs associated with a set of memory components of a memory sub-system. The processing device, in response to detecting the condition for performing the SG scan, accesses data associated with a plurality of memory cells of the set of memory components coupled to an individual SG of the set of SGs. The processing device adjusts a touch up (TU) program pulse based on the accessed data associated with the plurality of memory cells and applies the adjusted TU program pulse to the individual SG to place a threshold voltage (Vt) of the individual SG within a specified operating range.

Abstract: An optical fiber cladding optical filter includes an elongated capillary tube including an inner surface positioned surrounding an elongated optical fiber proximate or adjacent an exterior surface of the optical fiber and an outer surface positioned spaced from the exterior surface of the optical fiber. A grating formed on the outer surface of the elongated capillary tube aids in suppressing evanescent laser light that exits the optical fiber transverse to a longitudinal axis of the optical fiber. The elongated optical fiber and surrounding elongated capillary tube can include one or more curves along a length thereof to aid in the removal of one or more higher order laser modes as evanescent laser light that exits the optical fiber. The one or more curves can be received in a container to prevent or avoid evanescent laser exiting the optical fiber from propagating into an ambient environment.

Abstract: Methods, systems, and apparatuses include retrieving a failed bit count threshold using a current memory group for a portion of memory. A current offset value is retrieved using the current memory group. A memory group scan is performed on the portion of memory using the current offset value. A current failed bit count is determined using results of the memory group scan. A second offset value is retrieved using a second memory group for the portion of memory. A second memory group scan is performed on the portion of memory using the second offset value. A second failed bit count is determined using results of the second memory group scan. The portion of memory is allocated to a destination memory group using the current failed bit count, the second failed bit count, and the failed bit count threshold.

Abstract: Various embodiments described herein provide for performing a reset read operation on a memory device using a priority-based block pool, where the memory device can be part of a memory system. Various embodiments use the priority-based block pool to facilitate use of different multi-block options for performing reset read operations for different groups of consecutive blocks (e.g., during a ganged reset read or a group-based reset read (GRR) process).

Abstract: Methods, systems, and apparatuses include probabilistically determining a read operation number using a window size. A read command is received from a host device by a memory subsystem. A memory address is determined using the read command. It is determined that the read command corresponds to the read operation number. The memory address is flagged to have a select gate of the memory address scanned. The select gate of the memory address is scanned in response to flagging the memory address.

Abstract: Methods, systems, and apparatuses include receiving, by a memory subsystem, a read command from a host device to read data from a memory portion of the memory subsystem. It is determined that the memory portion includes a partial block. A memory bin is determined for the memory portion in response to determining that the memory portion includes the partial block. A position is determined for the memory portion. A voltage offset is applied to a read voltage for the memory portion using the memory bin and the position.

Abstract: A two-dimensional (2D) fiber collimator array may include a fiber hole plate, fibers, a grooved spacer, and a microlens array (MLA). Rows of holes may extend through the fiber hole plate from a fiber hole plate first side to a fiber hole plate second side. Each fiber may extend through a respective hole of the fiber hole plate and may include a fiber end face at the fiber hole plate second side. The grooved spacer may include a grooved spacer first side and a grooved spacer second side. The grooved spacer first side may include a plurality of microgrooves. Each microgroove may include an incident surface angled with respect to the grooved spacer first side. An adhesive may couple the grooved spacer first side to the fiber hole plate second side. A refractive index of the adhesive may substantially match a refractive index of the fiber end faces.

Abstract: The present disclosure configures a system component, such as memory sub-system controller, to perform empty page scan operations. The controller, in response to a request to perform an empty page scan operation, identifies a portion of a set of memory components that is empty and ready to be programmed. The controller generates an order in which to perform the empty page scan operation for a plurality of regions of the identified portion of the set of memory components. The controller determines whether a first region of the plurality of regions in the order fails the empty page scan operation before a second region of the plurality of regions is scanned. The controller terminates the empty page scan operation early to prevent performing the empty page scan operation for one or more remaining regions of the plurality of regions of the identified portion.

Abstract: A glycosyltransferase mutant and a method for catalytic synthesis of rebaudioside M using the glycosyltransferase mutant are provided. The glycosyltransferase mutant is obtained through mutation based on a glycosyltransferase amino acid sequence shown in SEQ ID NO: 1, and can be produced by inducing expression in a mutant strain. The glycosyltransferase mutant can be used as a catalyst for enzymatic catalytic synthesis of 12.8 g/LRebM from 20 g/LRebE. Michaelis constants (a kinetic parameter) of the glycosyltransferase mutant S195Q for rebaudioside E and rebaudioside D are 56.34±2.02 ?M and 214.48±14.54 ?M, respectively, which are ? and ? of a Michaelis constant of a wild-type (WT) glycosyltransferase, respectively.

Abstract: This disclosure is directed to a system for performing read error handling. The system selects a set of read count (RC) thresholds using a configuration parameter that reduces periodic scan intervals. The system, in response to selecting the set of RC thresholds, generates a read disturb handling (RDH) scan configuration table based on the set of RC thresholds and performs a set of RDH scans on a portion of a memory device in response to determining that a current RC of the portion corresponds to an individual RC threshold stored in the RDH scan configuration table.

Abstract: A system including a memory device and an operatively coupled processing device to perform operations including: responsive to detecting a power-up event, performing a first read strobe on a first set of a plurality of memory cells addressable by a first wordline, determining a value of a conductivity metric reflecting conductive states of one or more bitlines connected to the first set of the plurality of memory cells, determining, based on the value of the conductivity metric, a read level offset value for a second wordline, wherein the second wordline is adjacent to the first wordline, performing, using the read level offset value, a second read strobe on the second wordline, and responsive to determining that a value of a quality metric produced by the second read strobe satisfies a quality criterion, indicating that a programming operation performed on the second wordline was completed before a power off event.

Abstract: A system and method are provided for retiring blocks in a memory device. The system and method perform a first select gate (SG) scan operation on a memory portion of a memory device. After performing the first SG scan operation, the system and method selectively perform a second SG scan operation on the memory portion, the second SG scan operation having different verification operations than the first SG scan operation. The system and method selectively perform one or more SG maintenance operations on the memory portion based on a result of performing at least one of the first SG scan operation and the second SG scan operation on the memory portion.

Abstract: A system and method are provided for retiring blocks in a memory device. The system and method perform a first select gate (SG) scan operation on a memory portion of a memory device that has been erased according to a first type of erase operation. The system and method, in response to determining that the memory portion fails the first SG scan operation, perform a second SG scan operation on the memory portion, the second SG scan operation having different verification operations than the first SG scan operation. The system and method selectively perform a second type of erase operation on the memory portion based on a result of performing the second SG scan operation on the memory portion.

Abstract: This disclosure is directed to a system for performing read disturb handling. The system tracks read stress counts for a plurality of word lines (WLs) in a portion of the memory device. The system, in response to determining that a read count (RC) threshold for the portion of the memory device has been reached, selectively adds one or more WLs from the plurality of WLs to a WL list comprising a set of predefined mandatory WLs based on the read stress counts of the one or more WLs. The system performs a read disturb handling (RDH) operation on WLs in the WL list.

Abstract: Exemplary methods, apparatuses, and systems including a scan manager for dynamic read disturb handling using selective scanning. The scan manager reads a list of wordlines to be scanned during a read disturb handling of a memory device. The memory device has separately accessible blocks of memory where each block of memory has a plurality of wordlines used to address a plurality of pages. Each block of memory is divided into a plurality of sub-blocks. The scan manager randomly selects a sub-block from the plurality of sub-blocks of a block of memory. The scan manager scans a page of the plurality of pages of a wordline from the list of wordlines of the selected sub-block during the read disturb handling.

Abstract: This disclosure is directed to a system for performing read error handling. The system tracks read count and temperature data for a portion of a memory device and, in response to determining that the read count for the portion transgresses a threshold, compares a current bin assignment that specifies a first set of read threshold offsets for reading data from the portion of the memory device with a target bin specified in a predefined table of bin assignments. The predefined table of bin assignments associates read counts and temperatures with corresponding target bin assignments. The system selectively performs bin calibration to selectively adjust a read threshold voltage offset to read data from the portion in response to comparing of the current bin assignment and the target bin and performs a read disturb handling (RDH) operation on the portion of the memory device using the selectively adjusted read threshold voltage offset.

Abstract: An apparatus that includes a set of memory components of a memory sub-system is disclosed for selectively adjusting a touch up program pulse of an SG. The memory sub-system includes a processing device that detects a condition for performing a select gate (SG) scan for a set of SGs associated with a set of memory components of a memory sub-system. The processing device, in response to detecting the condition for performing the SG scan, accesses data associated with a plurality of memory cells of the set of memory components coupled to an individual SG of the set of SGs. The processing device adjusts a touch up (TU) program pulse based on the accessed data associated with the plurality of memory cells and applies the adjusted TU program pulse to the individual SG to place a threshold voltage (Vt) of the individual SG within a specified operating range.

Abstract: A multi-dielet module is disclosed. In one embodiment, the module comprises an interposer and a substrate. The interposer is connected to at least one I/O dielet and at least one non-I/O dielet using micro-bump interconnect structures. The substrate is connected to the interposer using C4 bumps on one surface of the substrate and BGA interconnect structures on another. The at least one I/O dielet is configured to allow structural/scan test data from an external source to be communicated through the substrate and interposer to test I/Os of the at least one I/O dielet. The at least one I/O dielet is configured to allow the structural/scan test data to be communicated from the at least one I/O dielet to the that at least one non-I/O dielet using a chip-to-chip (C2C) interface and the micro-bump interconnect structures of the at least one I/O dielet and the at least one non-I/O dielet.

Abstract: Methods, systems, and apparatuses include probabilistically determining a read operation number using a window size. A read command is received from a host device by a memory subsystem. A memory address is determined using the read command. It is determined that the read command corresponds to the read operation number. The memory address is flagged to have a select gate of the memory address scanned. The select gate of the memory address is scanned in response to flagging the memory address.