Abstract: A time-to-digital converter includes N stages of converting circuits, where N2, and N is an integer. Each stage of the converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of the converting circuit outputs a delayed signal of the stage of the converting circuit; and the arbiter in each stage of the converting circuit receives a sampling clock and the delayed signal of the stage of the converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of the converting circuit. The first delayer in each stage of the converting circuit includes at least one first delay cell circuit with a first time unit. The first delayer in any stage of the converting circuit includes a less number of first delay cell circuits than the first delayer in a next stage of the converting circuit.

Abstract: Embodiments of the present invention provide a data read/write method and apparatus, a storage device, and a computer system, so as to reduce completion time of a data read/write operation in a multi-core computer system. The method includes: determining, by a host device, N cores used for executing a target process, where the N cores are in a one-to-one correspondence with N execution threads included in the target process; grouping the N execution threads to determine M execution thread groups, and allocating an indication identifier to each execution thread group; and sending M data read/write instructions to a storage device, where each data read/write instruction includes an indication identifier of a corresponding execution thread group.

Abstract: An oscillator, including a resonance circuit, a cross coupled current source circuit, and a positive feedback circuit coupled between the current source circuit and the resonance circuit, where the resonance circuit is configured to generate a differential oscillation signal having a first oscillation frequency, the positive feedback circuit is configured to receive the differential oscillation signal, and amplify a gain of the differential oscillation signal to obtain a differential output oscillation signal, and the current source circuit is configured to provide an adjustable bias current for the resonance circuit and the positive feedback circuit.

Abstract: A controller for a valve assembly that is configured to meet requirements for use in hazardous areas. These configurations may regulate flow of instrument air to a pneumatic actuator to operate a valve. The controller may comprise enclosures, including a first enclosure and a second enclosure, each having a peripheral wall forming an interior space, and circuitry comprising a barrier circuit disposed in the interior space of one of the enclosures that power limits digital signals that exits that enclosure. In one example, the peripheral wall of enclosures are configured to allow instrument air into the interior space of the first enclosure but to prevent instrument air from the interior space of the second enclosure.

Abstract: A method for scheduling a terminal device comprises performing blind detection on N subframes by using at least one codebook and a pilot corresponding to the codebook, and determining, according to a blind detection result, a first pilot set corresponding to each codebook in each subframe, where correct terminal data cannot be obtained by performing blind detection by using a pilot in the first pilot set and a corresponding codebook. The method comprises determining, according to the first pilot set corresponding to each codebook, a second pilot set corresponding to each codebook, where a pilot in the second pilot set is a pilot that is in the first pilot set and that has already been sent by the terminal device, and determining a to-be-used transmission mode according to the second pilot set corresponding to each codebook in each subframe, where different transmission modes correspond to different spectrum multiplex rates.

Abstract: A board-level assembly that is useful to expand functions of a valve positioner on a valve assembly. The board-level assembly can incorporate a main circuit board and a peripheral “smart” circuit board. The main circuit board may be configured to communicate with the smart circuit board, find a storage memory on the second circuit board, retrieve data from the storage memory, and use the data to configure functions on the first circuit board. In one implementation, the smart circuit board can release and engage the main circuit board. This configuration can allow different configurations of the smart circuit board to swap into the board-level assembly, each of the different configurations providing data the main circuit board can exploit to change the functions of the valve positioner.

Abstract: The present invention discloses a solution including: receiving channel quality fed back by at least two user terminals; determining, according to the received channel quality fed back by the at least two user terminals, a user terminal that needs to be served by each transmit antenna of a base station device; for user terminals served by a same transmit antenna, configuring, according to channel quality fed back by the user terminals served by the same transmit antenna, a constellation expansion modulation scheme for each user terminal served by the same transmit antenna, and determining an intra-stream power allocation factor and an initial phase rotation coefficient of the transmit antenna; and processing, by using the modulation scheme, a signal to be sent to the user terminal, and transmitting the processed signal to the user terminal according to the intra-stream power allocation factor and the initial phase rotation coefficient.

Abstract: A time-to-digital converter including N stages of converting circuits, where N?2, and N is an integer. Each stage of converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of converting circuit outputs a delayed signal of the stage of converting circuit; and the arbiter in each stage of converting circuit receives a sampling clock and the delayed signal of the stage of converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of converting circuit. Output signals of the N stages of converting circuits form a non-linear binary number, to indicate a time difference between a clock signal and a reference signal.

Abstract: A system and method for managing resources in a distributed computer system that includes at least one resource pool for a set of virtual machines (VMs) utilizes a set of desired individual VM-level resource settings that corresponds to target resource allocations for observed performance of an application running in the distributed computer system. The set of desired individual VM-level resource settings are determined by constructing a model for the observed application performance as a function of current VM-level resource allocations and then inverting the function to compute the target resource allocations in order to meet at least one user-defined service level objective (SLO). The set of desired individual VM-level resource settings are used to determine final RP-level resource settings for a resource pool to which the application belongs and final VM-level resource settings for the VMs running under the resource pool, which are then selectively applied.

Abstract: A usage frequency attribute is determined for each biometric feature in a biometric feature database. The usage frequency attribute indicates a matching success frequency of matching the biometric feature to a user having the biometric feature. The biometric features of the user are sorted in descending order of the usage frequency attribute. The sorting is based on a descending order of the usage frequency attributes for a given user. The biometric features in the biometric feature database are stored in descending order. The storing includes providing prioritized access to the biometric feature having a highest value of the usage frequency attribute so that the biometric feature is selected first in response to a request for the biometric feature of the user.

Abstract: A valve assembly that is configured to wirelessly transmit data using near-field communication protocols. The embodiments may include a passive, NFC-enabled device disposed inside of a controller (or “valve positioner”). This NFC-enabled device can operate as a communication “port” to allow data exchange with a handheld computing device, like a smartphone or tablet. This feature can afford end users (e.g., technicians) ready access to data on the valve assembly via the handheld computing device.

Abstract: A data writer may be constructed and operated as part of a data storage device. The data writer can be positioned proximal a data storage medium. The data writer may have a write pole positioned adjacent a writer coil with the writer coil having a plurality of turns. A controller that is connected to each turn can be adapted to selectively activate less than all the coil turns in response to the data writer being positioned over a first portion of a data storage medium and selectively activate all of the coil turns in response to the data writer being positioned over a second portion of the data storage medium.

Abstract: Aspects describe a vertical metal-oxide thin-film transistor with multiple-junction channel and a method to fabricate the same. In one example, the vertical transistor comprises a substrate, an interconnecting electrode and source and drain electrodes separated by a spacer. The vertical transistor also includes a metal oxide active layer formed over the interconnecting electrode and the source and drain electrodes and adjacent to the interconnecting electrode, the spacer, and the source and drain electrodes. Further, the vertical transistor includes a gate stack adjacent to the metal oxide active layer and a multiple-junction channel region provided within the metal oxide active layer adjacent to the gate stack.

Abstract: Technologies are described for evaluation of server performance through a single value SPI. Server performance dimensions to be used in overall server performance evaluation may be determined and monitored through continuous monitoring or sampling. The dimensions may include, but are not limited to, processor usage, memory usage, input/output usage, network usage, response time, latency, and similar parameters. A threshold value that identifies an average performance value for each dimension over a predefined time period may be determined for each dimension. A performance index may be determined for each dimension normalized by the corresponding threshold value. The SPI may be determined based on an averaging of the performance indices of the one or more dimensions and an alert or a report may be generated and/or a server operation may be adjusted based on an evaluation of the SPI.

Abstract: This disclosure relates generally to the three-dimensional (3D) integrated thin-film transistors (TFTs) with silicon and metal-oxide (MO) semiconductors as the active layers. In one or more embodiments, an apparatus is provided that comprises a first transistor comprising a silicon active layer, and a second transistor comprising a metal oxide active layer. The second transistor is vertically stacked on the first transistor, and the first transistor and the second transistor share a gate electrode formed between the silicon active layer and the metal oxide active layer. With these embodiments, the gate electrode corresponds to a top gate of the first transistor and a bottom gate of the second transistor.

Abstract: An apparatus is provided that includes a substrate and source and drain regions within an annealed active layer having resulted from an annealing of an active layer comprising metal-oxide and formed on the substrate, and an impermeable layer over the source and drain regions of the annealed active layer, wherein the annealing resulting in the annealed active layer was performed with the impermeable layer over portions of the active layer corresponding to the source and drain regions, thereby resulting in a reduction of a resistivity of the source and drain regions of the annealed active layer relative to the active layer. In another aspect, a junctionless transistor is provided wherein the entire active area has a low resistivity based on annealing of an active layer including metal oxide while uncovered or at least partially covered with layers of various gas permeability under oxidizing or non-oxidizing conditions.

Abstract: A method includes depositing a layer of pole material on a substrate. The layer of pole material has a bottom surface that is adjacent to the substrate and a top surface that is opposite the bottom surface. A masking material is deposited over a portion of the top surface. Material from the pole material unprotected by the masking material is removed to form a write pole having first and second side walls. At least a portion of a trench formed by removal of the material from the layer of pole material is filled with a sacrificial material. The mask and a portion of the write pole at the top surface are removed to form a beveled trailing edge surface. The sacrificial material is then removed. Front shield gap material is deposited over the beveled trailing edge surface and over portions of the side walls.

Abstract: Thin film transistors are provided that include a metal oxide active layer with source and drain regions having a reduced resistivity relative to the metal oxide based on doping of the source and drain regions at room temperature. In an aspect, a transistor structure is provided, that includes a substrate, and source and drain regions within a doped active layer having resulted from doping of an active layer comprising metal-oxide and formed on the substrate, wherein the doped active layer was doped at room temperature and without thermal annealing, thereby resulting in a reduction of a resistivity of the source and drain regions of the doped active layer relative to the active layer prior to the doping. In an aspect, the source and drain regions have a resistivity of about 10.0 m?·cm after being doped with stable ions and without subsequent activation of the ions via annealing.

Abstract: The present disclosure discloses a tripod universal joint fairway heat treatment device. A magnetizer includes a middle induction area and two-end induction areas, wherein the middle induction area includes magnetic conductive sheets stacked together; and the two-end induction areas include magnetic conductive sheets and magnetic conductive insulation sheets crosswise stacked together. Controllable deformation of an inner cavity fairway of a tripod universal joint during intermediate frequency quenching is realized by changing an arrangement form of the magnetic conductive sheets in the magnetizer, thereby avoiding a condition that three pivot shafts and bearing rings cannot be installed due to excessive deformation at a fairway opening after quenching, and greatly improving a qualified rate of products and safety performance of the products during use.

Abstract: Embodiments relate to a data transmission method. A relay node receives information that is about an SCMA codebook used by the relay node and that is sent by a destination node. The relay node receives two or more source signals sent by two or more source nodes. The relay node performs network coding on the received two or more source signals. The relay node performs SCMA codebook mapping on a signal obtained after the network coding, so as to obtain at least two modulation symbols. The relay node sends to the destination node, the at least two modulation symbols obtained after the SCMA mapping.