Abstract: Embodiments of the present disclosure include a semiconductor device having stacked transistors with a bottom transistor below a top transistor, the bottom transistor having a first bottom source/drain region and a second bottom source/drain region. A first backside contact is connected to the first bottom source/drain region and a frontside wiring. A second backside contact is connected to the second bottom source/drain region and a backside power plane. A connection via is formed through the backside power plane to connect a top source/drain region of the top transistor to a backside power rail.

Abstract: A semiconductor structure may include a first pass gate oriented along a first line. A semiconductor structure may include a first inverter in line with the first line. The first inverter may include a first channel region, a second channel region stacked above the first channel region. The semiconductor structure may also include an inverter gate around the first channel region and the second channel region, with a gate extension above the pass gate.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads; and a metal body that electrically connects the pads. The metal body includes a first portion that is embedded in the first layers, made of a first plurality of discrete segments; a second portion that is embedded in the second layers, made of a second plurality of discrete segments, of which a first is electrically connected to the first pad and a second is electrically connected to the second pad; and a plurality of vias that interconnect the first and second portions. Breaking any of the vias reduces the electrical connectivity between the pads.

Abstract: An exemplary structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The body includes a first portion that is embedded in the plurality of first dielectric layers. The first portion comprises a first layer of first metal. The body further includes a second portion that is embedded in the plurality of second dielectric layers. The second portion comprises a first layer of second metal. A plurality of vias interconnect the first portion to the second portion through the active device layer. The first layer of the first portion mechanically connects the plurality of vias and the first layer of the second portion mechanically connects the plurality of vias.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads at a top side of the second layers; a first metal body electrically connected to the first pad; and a second metal body electrically connected to the second pad. The bodies, with the layers, form a capacitor that couples the pads. Each of the bodies includes: an upper portion that is embedded in the plurality of second layers and is directly connected to a respective one of the first and second pads; a lower portion that is embedded in the plurality of first layers; and a via that connects the upper to the lower portion through the active layer.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the semiconductor substrate; an active device layer at a top side of the plurality of first dielectric layers; and a plurality of second dielectric layers at a top side of the active device layer. Also included are at least hundreds of metal bodies, each of which is on the order of about 10 nm to about 1000 nm in critical dimension and includes: a first metal plate, at a first level in the plurality of first dielectric layers that is adjacent to the active device layer; a second metal plate, at a second level in the plurality of second dielectric layers that is adjacent to the active device layer; and a first plurality of vias that connect the first metal plate to the second metal plate through the active device layer.

Abstract: A main beam for wind turbine blade, comprising: one or more carbon fiber pultruded bodies, wherein, each carbon fiber pultruded body comprising one or more carbon fiber pultruded sheets, the carbon fiber pultruded sheets are stacked along the thickness direction and are formed by curing a first infusion material, wherein a glass fiber infusion material is arranged between every two carbon fiber pultruded sheets; one or more inlays, which are arranged adjacent to the carbon fiber pultruded body in a direction perpendicular to the thickness direction of the main beam; one or more overlays, which cover the carbon fiber pultruded bodies and/or the inlays on both sides in the thickness direction of the main beam; and a second infusion material, which impregnates carbon fiber pultruded bodies, the inlays and the overlays.

Abstract: A device and a method for separating materials. The device includes a material receiving plate arranged to receive materials to be separated, a first pair of supporting members coupled to opposite sides of the material receiving plate via respective pendulum rods, and a second pair of supporting members coupled to the opposite sides of the material receiving plate via respective pendulum rods and spaced apart from the first pair of supporting members. The device also includes a driving mechanism and a transmission mechanism.

Abstract: A main beam for wind turbine blade, comprising: one or more carbon fiber pultruded bodies, wherein, each carbon fiber pultruded body comprising one or more carbon fiber pultruded sheets, the carbon fiber pultruded sheets are stacked along the thickness direction and are formed by curing a first infusion material, wherein a glass fiber infusion material is arranged between every two carbon fiber pultruded sheets; one or more inlays, which are arranged adjacent to the carbon fiber pultruded body in a direction perpendicular to the thickness direction of the main beam; one or more overlays, which cover the carbon fiber pultruded bodies and/or the inlays on both sides in the thickness direction of the main beam; and a second infusion material, which impregnates carbon fiber pultruded bodies, the inlays and the overlays.

Abstract: The present application discloses a metering system for calculating a real-time profit or loss of a gas station, including a metering module, a level gauge of the oil tank, and a communication management machine with a built-in data processing module; the metering module and the level gauge are respectively communicated with the communication management machine; the oil tank, an oil pipeline of the oil tank and an oil inlet of the fuel dispenser are respectively provided with a sensor array module for collecting density data of the oil therein; the sensor array module includes a plurality of oil density sensors; the sensor array modules are communicated with the communication management machine; the built-in data processing module receives and processes data from the metering module, the level gauge and the sensor array modules respectively.

Abstract: The present application discloses a metering system for calculating a real-time profit or loss of a gas station, including a metering module, a level gauge of the oil tank, and a communication management machine with a built-in data processing module; the metering module and the level gauge are respectively communicated with the communication management machine; the oil tank, an oil pipeline of the oil tank and an oil inlet of the fuel dispenser are respectively provided with a sensor array module for collecting density data of the oil therein; the sensor array module includes a plurality of oil density sensors; the sensor array modules are communicated with the communication management machine; the built-in data processing module receives and processes data from the metering module, the level gauge and the sensor array modules respectively.

Abstract: An extreme ultraviolet (EUV) mask including an absorber structure is disclosed. The absorber structure may include at least one slanted and/or concave sidewall. The absorber structure may include a sidewall including a step. A method of forming an absorber for an EUV mask is disclosed. The method may include etching an absorber layer using a mask to form an absorber structure having a sidewall wherein an outer edge of the top surface of the sidewall is closer to a central vertical axis of the absorber structure than an outer edge of the bottom surface of the sidewall. The method may include performing additional etching steps to form a step along the sidewall of the absorber structure. The etching may include combinations of anisotropic etching in different directions, and/or isotropic etching. The method may include etching an absorber layer including multiple absorber layers having different material properties on the ML reflector.

Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.

Abstract: An extreme ultraviolet (EUV) mask including an absorber structure is disclosed. The absorber structure may include at least one slanted and/or concave sidewall. The absorber structure may include a sidewall including a step. A method of forming an absorber for an EUV mask is disclosed. The method may include etching an absorber layer using a mask to form an absorber structure having a sidewall wherein an outer edge of the top surface of the sidewall is closer to a central vertical axis of the absorber structure than an outer edge of the bottom surface of the sidewall. The method may include performing additional etching steps to form a step along the sidewall of the absorber structure. The etching may include combinations of anisotropic etching in different directions, and/or isotropic etching. The method may include etching an absorber layer including multiple absorber layers having different material properties on the ML reflector.

Abstract: A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.

Abstract: A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.

Abstract: A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.

Abstract: Various embodiments include measurement structures and methods for measuring integrated circuit (IC) images. In some cases, a measurement structure for use in measuring an image of an IC, includes: a first section having a positive shift spacing pattern; a second section, on an opposite side of the measurement structure, having a negative shift spacing pattern; and a third section having a reference spacing pattern for calibrating a measurement from at least one of the first section or the second section.

Abstract: Various embodiments include measurement structures and methods for measuring integrated circuit (IC) images. In some cases, a measurement structure for use in measuring an image of an IC, includes: a first section having a positive shift spacing pattern; a second section, on an opposite side of the measurement structure, having a negative shift spacing pattern; and a third section having a reference spacing pattern for calibrating a measurement from at least one of the first section or the second section.

Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.