Abstract: A voter-based method of controlling a redundancy is provided, including acquiring a processing element array in a target hardware, wherein the processing element array includes a plurality of processing elements, selecting a plurality of groups of processing elements from the processing element array so as to generate a voter set, wherein a corresponding voter is generated for each group of the plurality of groups of processing elements, and the corresponding voter configured to perform a voting operation in a redundancy control, acquiring, in response to a message indicating a fault state of a detected voter, a target voter from the voter set so as to replace the detected voter, and re-performing the voting operation in the redundancy control by using the target voter. An electronic device and a storage medium are further provided, which are implemented based on the processing element array of the target hardware.

Abstract: A method for a compilation, an electronic device and a readable storage medium are provided. The method for a compilation includes analyzing source program data to determine a target irregular branch, generating an update data flow graph according to the target irregular branch, and mapping the update data flow graph to a target hardware to complete the compilation.

Abstract: The disclosure provides a processor checking method, a checking device and a checking system. The method includes acquiring a first access record of the processor to a first memory during a running process, the first access record including reading-operation information; acquiring a second access record of a checking device to a second memory during a replay process, the second access record including first reading-operation information, the first reading-operation information being reading-operation information corresponding to a case in which a first access of the checking device to a same address during the replay process is a reading operation, and determining, based on the first access record and the second access record, whether or not the processor reads during the running process a memory address that is not any one of addresses included in the second access record.

Abstract: The present disclosure provides a processor checking method, a checking device and a checking system. The method includes acquiring an access record to a memory by a processor during a running process, the access record includes a read operation information and a corresponding time information, determining whether there is a read operation information corresponding to a high access authority in the access record, and when there is a read operation information corresponding to a high access authority, determining whether the read operation information corresponding to the high access authority belongs to an unauthorized operation. According to embodiments of the present disclosure, the behavior of the processor reading data from the memory is checked and analyzed, thereby preventing the security problems caused by malicious use of unauthorized reading operation.

Abstract: The present disclosure provides a method and an apparatus for processing concurrent transactions, and a non-transitory computer readable storage medium. The method includes: determining whether a two-dimensional digraph for a set of concurrent transactions has a cyclic structure, wherein the set of concurrent transactions comprises a transaction to be committed and at least one committed transaction, the two-dimensional digraph comprises a plurality of nodes corresponding respectively to the transactions in the set, and directed edges between the nodes of the two-dimensional digraph indicate a serializability relation among the transactions in the set; aborting the transaction to be committed if it is determined that the two-dimensional digraph has the cyclic structure; and committing the transaction to be committed if it is determined that the two-dimensional digraph does not have the cyclic structure. Embodiments of the present disclosure can improve the performance of a concurrent system.

Abstract: The present disclosure provides a system and method of implementing a security algorithm using a reconfigurable processor, the method including: determining a plurality of sub-algorithms for constructing the security algorithm; and configuring the reconfigurable processor to implement the security algorithm according to a first configuration information of each sub-algorithm of the plurality of sub-algorithms and a first combination configuration information indicating a combination connection relationship of each of the sub-algorithms. The present disclosure also provides a system and method of implementing a decryption algorithm using a reconfigurable processor.

Abstract: The present disclosure provides a method and an apparatus for processing concurrent transactions, and a non-transitory computer readable storage medium. The method includes: determining whether a two-dimensional digraph for a set of concurrent transactions has a cyclic structure, wherein the set of concurrent transactions comprises a transaction to be committed and at least one committed transaction, the two-dimensional digraph comprises a plurality of nodes corresponding respectively to the transactions in the set, and directed edges between the nodes of the two-dimensional digraph indicate a serializability relation among the transactions in the set; aborting the transaction to be committed if it is determined that the two-dimensional digraph has the cyclic structure; and committing the transaction to be committed if it is determined that the two-dimensional digraph does not have the cyclic structure. Embodiments of the present disclosure can improve the performance of a concurrent system.

Abstract: A task allocating method for a reconfigurable processing system is provided by the present disclosure. The method includes determining a use status of a hardware processing resource of the reconfigurable processing system. The hardware processing resource includes m task channels and a reconfigurable computing array, and one task channel controls at least one operator in the reconfigurable computing array at a time to process one task. The number m is a positive integer and allocating a first task in n tasks to be processed according to the use status of the hardware processing resource, so that at least one task channel in the m task channels controls the reconfigurable computing array to process simultaneously at least one task which includes the first task, where the number n is a positive integer. A task allocating system for a reconfigurable processing system is also provided by the present disclosure.

Abstract: A method for processing an asynchronous event by a checking device and a checking device are provided, the method including: obtaining an instruction position where a checked processor executes an asynchronous event during a target running process; and executing the asynchronous event at the instruction position during executing a task of the target running process in a manner conforming to predefined behavior, wherein the predefined behavior is a hardware behavior standard of the processor. Obtaining the instruction position and executing the asynchronous event at the instruction position may cause the checking device and the checked processor to process the same asynchronous event at the same instruction position. In this way, during performing security checking on a processor, the method and the device according to the embodiments of the present disclosure may be used to eliminate the influence of the uncertainty factor of the asynchronous event.

Abstract: The disclosure provides an input and output recording device and method, CPU and data read and write operation method thereof. The input and output recording device is provided between a central processor CPU and a peripheral, and is configured to record data read and write operations between the CPU and the peripheral, wherein the data read and write operations comprise a data read and write operation initiated by the peripheral and a data read and write operation initiated by the CPU; the input and output recording device is further configured to request the CPU to process the data read and write operation initiated by the peripheral, and upon receiving an instruction sent by the CPU, send a data packet of the data read and write operation initiated by the peripheral to the CPU.

Abstract: A checking method for a processor is provided. The checking method first determines whether a checked processor satisfies a security-sensitive condition including one or more of security-sensitive instruction, processor running mode, security-sensitive input/output operation, security-sensitive application, and user-defined security level. Then, the checking method checks the checked processor according to a determination result, which further includes: when the checked processor satisfies the security-sensitive condition, checking the checked processor according to a first checking mode; and when the checked processor does not satisfy the security-sensitive condition, checking the checked processor according to a second checking mode; wherein for the same running process of the checked processor, a total checking length of the first checking mode is longer than that of the second checking mode. Also provided is a checking device for a processor and a checking system for a processor.

Abstract: The present disclosure discloses a processor security checking method, system and checking device. The processor security checking method includes: acquiring recording information of data read and write operations between a processor and a peripheral device, where the data read and write operation is a data read and write operation initiated by the processor or a data read and write operation initiated by the peripheral; and determining whether the processor is secure according to the recording information of the data read and write operation and an analysis result on the data read and write operation by the checking device. The embodiments of the present disclosure may detect hardware vulnerabilities and improve the security of hardware usage.

Abstract: A method and a device for processing an irregular application are disclosed. The method comprises: determining M classes of tasks of the irregular application; executing the M classes of tasks in parallel, wherein each task has an index respectively; for the i-th task in the x-th class of task of the M classes of tasks: when the i-th task is executed to a rendezvous, stalling the i-th task, and determining a rule corresponding to the i-th task; inspecting current state of the i-th task according to the rule corresponding to the i-th task so as to steer the continued execution of the i-th task. According to the embodiment of the present disclosure, irregular applications can be correctly and automatically executed with high performance in a manner of fine-grained pipeline parallelism.

Abstract: The present disclosure provides a system and method of implementing a security algorithm using a reconfigurable processor, the method including: determining a plurality of sub-algorithms for constructing the security algorithm; and configuring the reconfigurable processor to implement the security algorithm according to a first configuration information of each sub-algorithm of the plurality of sub-algorithms and a first combination configuration information indicating a combination connection relationship of each of the sub-algorithms. The present disclosure also provides a system and method of implementing a decryption algorithm using a reconfigurable processor.

Abstract: The disclosure provides a method, a checking device and a system for determining security of a processor. The method comprises: setting an initial running state of the checking device according to initial running state information of the processor during the target running process, and taking input information of the processor during the target running process as input information of the checking device; causing the checking device to execute a task of the target running process in a manner conforming to predefined behavior to obtain at least one of output information and final running state information of the checking device, wherein the predefined behavior is a standard of hardware behavior of the processor; and determining whether the processor is secure during the target running process according to at least one of the output information and the final running state information of the checking device when the checking device completes the task of the target running process.

Abstract: The disclosure provides a processor checking method, a checking device and a checking system. The method includes acquiring a first access record of the processor to a first memory during a running process, the first access record including reading-operation information; acquiring a second access record of a checking device to a second memory during a replay process, the second access record including first reading-operation information, the first reading-operation information being reading-operation information corresponding to a case in which a first access of the checking device to a same address during the replay process is a reading operation, and determining, based on the first access record and the second access record, whether or not the processor reads during the running process a memory address that is not any one of addresses included in the second access record.

Abstract: The present disclosure provides a processor checking method, a checking device and a checking system. The method includes acquiring an access record to a memory by a processor during a running process, the access record includes a read operation information and a corresponding time information, determining whether there is a read operation information corresponding to a high access authority in the access record, and when there is a read operation information corresponding to a high access authority, determining whether the read operation information corresponding to the high access authority belongs to an unauthorized operation. According to embodiments of the present disclosure, the behavior of the processor reading data from the memory is checked and analyzed, thereby preventing the security problems caused by malicious use of unauthorized reading operation.

Abstract: A method and a device for recording memory access operation information are provided by the present disclosure. The method comprises: recording memory access operations between a processor and a memory during a target running process to form an memory access sequence information of the target running process, wherein each of the memory access operation information in the memory access sequence information includes a memory access type, a memory access address and a memory access data; and determining a final storage state of the memory during the target running process according to the memory access sequence information of the target running process. According to the embodiments of the present disclosure, the final storage state of the memory during the target running process may be obtained by using less storage resources, and the hardware overhead is reduced.

Abstract: Provided is a method for generating configuration information of a dynamic reconfigurable processor. The dynamic reconfigurable processor includes a processing unit array, and the processing unit array includes a plurality of processing units. The method includes steps of: reading information of a task to be executed and generating an array configuration information top of the processing unit array according to the information; generating a plurality of processing unit configuration information corresponding to the plurality of processing units respectively according to the information; and assembling the array configuration information top and the plurality of processing unit configuration information.

Abstract: The present disclosure provides a reconfigurable processor and a timing control method thereof. The reconfigurable processor comprises a reconfigurable cell array (RCA) including a plurality of reconfigurable cells (RCs) and a control unit; the control unit is configured to generate and send a timing control information to the RCA; and the RCA is configured to execute an operation task according to the timing control information, wherein the RC in the RCA starts to execute an operation when receiving the timing control information, and delivers the timing control information to a next level of RC within the RCA according to a preset order after the operation is completed; and when the RCA completes the operation task corresponding to the timing control information, the RCA destroys the timing control information, wherein the operation task includes operations executed by each level of the RCs receiving the timing control information.