Abstract: We disclose a method for controlling access to an optically switched network, which connects N end-nodes, and is organized into a virtual data plane and a virtual control plane, which both communicate through the same underlying physical optical network. The virtual data plane provides any-to-all parallel connectivity for data transmissions among the N end-nodes, and the virtual control plane is organized as a ring that serially connects the N end-nodes, wherein a control token circulates around the ring. During operation, an end-node in the ring receives the control token, which includes a destination-busy vector with a busy flag for each of the N end-nodes. If the end-node has data to send and the busy flag for the destination end-node is not set, the system: sets the busy flag; commences sending the data to the destination end-node; and forwards the control token to a next end-node in the ring.

Abstract: An optically switched network system includes an optical switch with N inputs and N outputs that connects N end-nodes and is structured to transmit N wavelengths from each of the N inputs to each of the N outputs. The system includes a virtual data plane and a virtual control plane, which both communicate through the optical switch. The virtual data plane provides any-to-all parallel connectivity for data transmissions among the N end-nodes. The N end-nodes are partitioned into two or more subsets, wherein end-nodes in a given source subset transmit data to a given destination subset using wavelengths, which are not used by end-nodes outside of the given source subset to transmit data to the same given destination subset. The virtual control plane includes two or more rings associated with the two or more subsets of end-nodes. Each ring passes through a subset of end-nodes, and is used to communicate arbitration information among arbitration logic located at each end-node in the ring.

Abstract: An optically switched network system includes an optical switch with N inputs and N outputs that connects N end-nodes and is structured to transmit N wavelengths from each of the N inputs to each of the N outputs. The system includes a virtual data plane and a virtual control plane, which both communicate through the optical switch. The virtual data plane provides any-to-all parallel connectivity for data transmissions among the N end-nodes. The N end-nodes are partitioned into two or more subsets, wherein end-nodes in a given source subset transmit data to a given destination subset using wavelengths, which are not used by end-nodes outside of the given source subset to transmit data to the same given destination subset. The virtual control plane includes two or more rings associated with the two or more subsets of end-nodes. Each ring passes through a subset of end-nodes, and is used to communicate arbitration information among arbitration logic located at each end-node in the ring.

Abstract: We disclose a method for controlling access to an optically switched network, which connects N end-nodes, and is organized into a virtual data plane and a virtual control plane, which both communicate through the same underlying physical optical network. The virtual data plane provides any-to-all parallel connectivity for data transmissions among the N end-nodes, and the virtual control plane is organized as a ring that serially connects the N end-nodes, wherein a control token circulates around the ring. During operation, an end-node in the ring receives the control token, which includes a destination-busy vector with a busy flag for each of the N end-nodes. If the end-node has data to send and the busy flag for the destination end-node is not set, the system: sets the busy flag; commences sending the data to the destination end-node; and forwards the control token to a next end-node in the ring.

Abstract: A macro-switch is described. This macro-switch includes facing integrated circuits, one of which implements optical waveguides that convey optical signals, and the other which implements control logic, electrical switches and memory buffers at each of multiple switch sites. Moreover, the macro-switch has a fully connected topology between the switch sites. Furthermore, the memory buffers at each switch site provide packet buffering and congestion relief without causing undue scheduling/routing complexity. Consequently, the macro-switch can be scaled to an arbitrarily large switching matrix (i.e., an arbitrary number of switch sites and/or switching stages).

Abstract: A macro-switch is described. This macro-switch includes facing integrated circuits, one of which implements optical waveguides that convey optical signals, and the other which implements control logic, electrical switches and memory buffers at each of multiple switch sites. Moreover, the macro-switch has a fully connected topology between the switch sites. Furthermore, the memory buffers at each switch site provide packet buffering and congestion relief without causing undue scheduling/routing complexity. Consequently, the macro-switch can be scaled to an arbitrarily large switching matrix (i.e., an arbitrary number of switch sites and/or switching stages).

Abstract: A processor includes an instruction unit which provides instructions for execution by the processor, a decode/issue unit which decodes instructions received from the instruction unit and issues the instructions, and a plurality of execution queues coupled to the decode/issue unit. Each issued instruction from the decode/issue unit is stored into an entry of at least one queue of the plurality of execution queues, wherein each entry of the plurality of execution queues is configured to store an issued instruction and a duplicate indicator corresponding to the issued instruction which indicates whether or not a duplicate instruction of the issued instruction is also stored in an entry of another queue of the plurality of execution queues.

Abstract: A logic block is presented that generates avalanche criterion hash values using minimal logic. The logic block includes a first exclusive-OR function, a second exclusive-OR function, and an OR function. The first exclusive-OR function receives two input bits from a data packet and generates a linear output value based upon exclusive disjunction between the two input bits. The OR function receives two different input bits from the data packet and generates a first nonlinear output value based upon logical disjunction between the two different input bits. The second exclusive-OR function receives the linear output value and the first nonlinear output value, and generates a second nonlinear output value based upon exclusive disjunction between the linear output value and the first nonlinear output value. In turn, the second nonlinear output value is utilized to generate a hash value for the data packet.

Abstract: A processor includes an instruction unit which provides instructions for execution by the processor, a decode/issue unit which decodes instructions received from the instruction unit and issues the instructions, and a plurality of execution queues coupled to the decode/issue unit. Each issued instruction from the decode/issue unit is stored into an entry of at least one queue of the plurality of execution queues, wherein each entry of the plurality of execution queues is configured to store an issued instruction and a duplicate indicator corresponding to the issued instruction which indicates whether or not a duplicate instruction of the issued instruction is also stored in an entry of another queue of the plurality of execution queues.

Abstract: A logic block is presented that generates avalanche criterion hash values using minimal logic. The logic block includes a first exclusive-OR function, a second exclusive-OR function, and an OR function. The first exclusive-OR function receives two input bits from a data packet and generates a linear output value based upon exclusive disjunction between the two input bits. The OR function receives two different input bits from the data packet and generates a first nonlinear output value based upon logical disjunction between the two different input bits. The second exclusive-OR function receives the linear output value and the first nonlinear output value, and generates a second nonlinear output value based upon exclusive disjunction between the linear output value and the first nonlinear output value. In turn, the second nonlinear output value is utilized to generate a hash value for the data packet.

Abstract: A processor has a fetch unit and a branch execution unit. The fetch unit has a branch predictor. The branch predictor has a branch target buffer and a branch direction predictor. A wake value is a number of instruction fetches that is predicted to be performed after a fetch of a branch. Thus, for a first branch, for example, a first wake number is predicted. A low power mode of the branch predictor is enabled for a duration of the first wake value in response to hit in the branch target buffer in which the hit is in response to the first branch.

Abstract: A processor has a fetch unit and a branch execution unit. The fetch unit has a branch predictor. The branch predictor has a branch target buffer and a branch direction predictor. A wake value is a number of instruction fetches that is predicted to be performed after a fetch of a branch. Thus, for a first branch, for example, a first wake number is predicted. A low power mode of the branch predictor is enabled for a duration of the first wake value in response to hit in the branch target buffer in which the hit is in response to the first branch.