Abstract: A phase-locked loop has a phase detector that generates a phase difference signal, a circuit that generates a phase-locked loop output signal having a frequency that is a function of the phase difference signal, a frequency divider that receives the phase-locked loop output signal and generates therefrom a divided frequency signal. To substantially reduce variation in the duty cycle of the divided frequency signal, a comparison signal having one half the frequency of the divided frequency signal is generated. This may be performed by configuring a latch to toggle its output state once for every cycle of the divided frequency signal. To compensate for the additional division by two in the feedback path, the phase detector may use a dual-edge triggered latch to generate the phase difference signal so that it represents a phase difference between the reference signal and a signal having twice the frequency of the comparison signal.

Abstract: A phase-locked loop bandwidth is tuned to a desired level by operating the phase-locked loop in a phase-locked condition at a first frequency and applying a step response to the phase-locked loop by causing the phase-locked loop to begin locking to a second frequency that is different from the first frequency. A parameter is then detected that is related to the applied step response and that is indicative of whether the phase-locked loop bandwidth is at the desired level. The phase-locked loop bandwidth is adjusted, and the steps of operating at the first frequency, applying the step response, detecting the parameter and adjusting the phase-locked loop bandwidth are repeated until the phase-locked loop bandwidth is at the desired level. Where the desired bandwidth level for tuning is not the operational bandwidth, the phase-locked loop bandwidth is further adjusted by a predetermined amount, thereby tuning the phase-locked loop bandwidth to an operational level.