Patents by Inventor Leif Paulson

Leif Paulson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973105
    Abstract: An integrated circuit structure comprises at least one metal gate formed in a first dielectric layer, the at least one metal gate comprising a workfunction layer and the gate oxide layer along sidewalls of the first dielectric layer. A field effect (FE) dielectric layer dielectric layer is above the first dielectric layer of the at least one metal gate. A precision resistor comprising a thin-film metallic material is formed on the FE dielectric layer above the at least one metal gate and extending laterally over the at least one metal gate.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Bernhard Sell, Leif Paulson, Kinyip Phoa, Shi Liu
  • Publication number: 20200105861
    Abstract: An integrated circuit structure comprises at least one metal gate formed in a first dielectric layer, the at least one metal gate comprising a workfunction layer and the gate oxide layer along sidewalls of the first dielectric layer. A field effect (FE) dielectric layer dielectric layer is above the first dielectric layer of the at least one metal gate. A precision resistor comprising a thin-film metallic material is formed on the FE dielectric layer above the at least one metal gate and extending laterally over the at least one metal gate.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Inventors: Chieh-Jen KU, Bernhard SELL, Leif PAULSON, Kinyip PHOA, Shi LIU
  • Patent number: 8394687
    Abstract: The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: March 12, 2013
    Assignee: Intel Corporation
    Inventors: Pushkar Ranade, Keith Zawadzki, Leif Paulson
  • Publication number: 20090090982
    Abstract: The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant.
    Type: Application
    Filed: December 10, 2008
    Publication date: April 9, 2009
    Inventors: Pushkar Ranade, Keith Zawadzkl, Leif Paulson
  • Publication number: 20080237661
    Abstract: The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Pushkar Ranade, Keith Zawadzki, Leif Paulson