Abstract: A phase detector is applied for detecting the phase difference between a data signal and a clock signal, and outputting a first up signal whose pulse width is between 1/2 and 3/2 period of the clock signal, a first down signal, a second down signal, and a second up signal whose periods are equal to the period of the clock signal to a charge pump. The pulse width of the first up signal varies with the difference between the falling edge of the clock signal and the data signal. Besides, the falling edge of the first up signal of the invention is aligned to the falling edge of the clock signal, and is unrelated to the pulse of the data signal. The invention utilizes the up signal and down signal which are more accurate to resolve the unlock problem due to the divergence of the phase error signal.

Abstract: A data recovery device using a sampling clock with a half frequency of data rate is disclosed, which includes a phase detection circuit, a charge pump and a double clock frequency oscillation circuit. The phase detection circuit receives a data signal and a first clock signal for generating an up-adjustment signal and a down-adjustment signal. The charge pump generates a control voltage in accordance with the up- and down-adjustment signals. The double clock frequency oscillation circuit receives the control voltage for generating the first clock signal with adjustment phase. The invention uses the sampling clock with a half frequency of the data rate not only reduces the die size, but also reduces the power consumption.

Abstract: A phase detector is applied for detecting the phase difference between a data signal and a clock signal, and outputting a first up signal whose pulse width is between ½ and {fraction (3/2)} period of the clock signal, a first down signal, a second down signal, and a second up signal whose periods are equal to the period of the clock signal to a charge pump. The pulse width of the first up signal varies with the difference between the falling edge of the clock signal and the data signal. Besides, the falling edge of the first up signal of the invention is aligned to the falling edge of the clock signal, and is unrelated to the pulse of the data signal. The invention utilizes the up signal and down signal which are more accurate to resolve the unlock problem due to the divergence of the phase error signal.

Abstract: A data recovery device using a sampling clock with a half frequency of data rate is disclosed, which includes a phase detection circuit, a charge pump and a double clock frequency oscillation circuit. The phase detection circuit receives a data signal and a first clock signal for generating an up-adjustment signal and a down-adjustment signal. The charge pump generates a control voltage in accordance with the up- and down-adjustment signals. The double clock frequency oscillation circuit receives the control voltage for generating the first clock signal with adjustment phase. The invention uses the sampling clock with a half frequency of the data rate not only reduces the die size, but also reduces the power consumption.