Patents by Inventor Leigh M. TRIBOLET

Leigh M. TRIBOLET has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11756889
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, Kevin McCarthy, Leigh M. Tribolet, Debendra Mallik, Ravindranath V. Mahajan, Robert L. Sankman
  • Publication number: 20230260914
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Inventors: Sanka GANESAN, Kevin MCCARTHY, Leigh M. TRIBOLET, Debendra MALLIK, Ravindranath V. MAHAJAN, Robert L. SANKMAN
  • Patent number: 11694959
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: July 4, 2023
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, Kevin McCarthy, Leigh M. Tribolet, Debendra Mallik, Ravindranath V. Mahajan, Robert L. Sankman
  • Publication number: 20210043570
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Sanka GANESAN, Kevin MCCARTHY, Leigh M. TRIBOLET, Debendra MALLIK, Ravindranath V. MAHAJAN, Robert L. SANKMAN
  • Publication number: 20210035911
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).
    Type: Application
    Filed: July 29, 2019
    Publication date: February 4, 2021
    Inventors: Sanka GANESAN, Kevin MCCARTHY, Leigh M. TRIBOLET, Debendra MALLIK, Ravindranath V. MAHAJAN, Robert L. SANKMAN
  • Patent number: 10290569
    Abstract: An apparatus, comprising a first platform comprising a first working surface having a first non-planar portion; and a second platform comprising a second working surface having a second non-planar portion, wherein: the second working surface is opposite the first working surface, a distance between the first working surface and the second working surface is adjustable, the first non-planar portion comprises a first curved portion, and the second non-planar portion comprises a second curved portion opposite the first curved portion.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Kyle Yazzie, Venkata Suresh R. Guthikonda, Patrick Nardi, Santosh Sankarasubramanian, Kevin Y. Lin, Leigh M. Tribolet, John L. Harper, Pramod Malatkar
  • Publication number: 20190103345
    Abstract: An apparatus, comprising a first platform comprising a first working surface having a first non-planar portion; and a second platform comprising a second working surface having a second non-planar portion, wherein: the second working surface is opposite the first working surface, a distance between the first working surface and the second working surface is adjustable, the first non-planar portion comprises a first curved portion, and the second non-planar portion comprises a second curved portion opposite the first curved portion.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Kyle YAZZIE, Venkata Suresh R. GUTHIKONDA, Patrick NARDI, Santosh SANKARASUBRAMANIAN, Kevin Y. LIN, Leigh M. TRIBOLET, John L. HARPER, Pramod MALATKAR