Abstract: A readout circuit (3) determines the level of a signal held in a memory cell array (1) and outputs a high- or low-level signal to a data line (D) according to the comparison result. The readout circuit (3) comprises a first readout circuit (3a) with high operating speed and a second readout circuit (3b) with low power consumption. A selecting circuit (4) selects either of the first and second readout circuits (3a, 3b) on the basis of a selection signal (S) and drives the selected circuit in synchronization with an enable signal (E). This achieves high-speed operation in applications or operating periods where high speed is required, and reduces unnecessary power consumption in applications or operating period where high speed is not required. As a result, unnecessary power consumption in read operation is reduced.