Abstract: An out-of-band updating method and system of an Expander, applied to a controller connected to the expander by means of a communication bus. The method comprises: receiving firmware updating data sent by a user (S101); fragmenting the firmware updating data (S102); and only when determining that the expander is in an idle state, sending the fragmented data until each piece of data is sent to the Expander, such that the expander completely receiving the firmware updating data completes updating by restarting (S103). The data transmission speed is facilitated to be improved, the normal operation of a service is ensured, and the conditions of influencing state monitoring and log loss are avoided.

Abstract: A method and device for detecting a memory downgrade error. The method comprises: capturing and analyzing a memory error by means of an operating system (OS); sending a memory downgrade error log to a management chip BMC on a server motherboard according to the analysis result; and after the BMC receives log information, detecting and locating an uncorrectable memory inspection error on the basis of an algorithm.

Abstract: A method and device for detecting a memory downgrade error. The method comprises: capturing and analyzing a memory error by means of an operating system (OS); sending a memory downgrade error log to a management chip BMC on a server motherboard according to the analysis result; and after the BMC receives log information, detecting and locating an uncorrectable memory inspection error on the basis of an algorithm.

Abstract: A hybrid heterogeneous host system, a resource configuration method and a task scheduling method are disclosed. The system includes: a basic unit, including: computing resource nodes, storage resource nodes and input/output I/O resource nodes; wherein multiple basic units are connected via a high-speed internetwork; and a software definition unit, configured to: when system resources are increased or reduced, extend the address space of an increased hardware resource to a current address space, or delete an address space of a reduced hardware resource from the current address space, and update a system resource view. Through the embodiments of the present invention, the extendibility of a tightly coupled shared memory system can be guaranteed, and the design complexity and cost of the multiway system also can be greatly reduced, which improves the flexibility and reusability of the system.

Abstract: A method and system for implementing a directory structure of a host system are disclosed. The method includes: multiple basic computing units interconnecting via a high speed internetwork to construct a system computing unit set; wherein each basic computing unit comprises a protocol processing chip and a system resource management firmware; and dividing a part implementing a logic function in the protocol processing chip into a static part and a dynamic part in advance, wherein the dynamic part can be reconstructed; constructing a system cache directory storage architecture through the dynamic part; and the system resource management firmware managing system resources by means of configuration.

Abstract: A method and system for implementing a directory structure of a host system are disclosed. The method includes: multiple basic computing units interconnecting via a high speed internetwork to construct a system computing unit set; wherein each basic computing unit comprises a protocol processing chip and a system resource management firmware; and dividing a part implementing a logic function in the protocol processing chip into a static part and a dynamic part in advance, wherein the dynamic part can be reconstructed; constructing a system cache directory storage architecture through the dynamic part; and the system resource management firmware managing system resources by means of configuration.

Abstract: A differential signal reversion and correction circuit and a method thereof are provided. The structures of the circuit include: a data frame sending module, when the link conditions are detected, the data frame sending module generates specific logic sequence and finishes the sending by a input/output port, such that a receiving side receives, processes and analyzes the sequence, and determination of link transmission conditions are achieved; a comparator of the receiving side, which receives sequence data, performs corresponding comparing, checking and feedback controlling, thereby achieving link detection and differential correction purpose; a reversion control signal generating module, which receives a comparison result of the comparator, generates corresponding control signal, and controls the link whether to perform reversion operation.

Abstract: A hybrid heterogeneous host system, a resource configuration method and a task scheduling method are disclosed. The system includes: a basic unit, including: computing resource nodes, storage resource nodes and input/output I/O resource nodes; wherein multiple basic units are connected via a high-speed internetwork; and a software definition unit, configured to: when system resources are increased or reduced, extend the address space of an increased hardware resource to a current address space, or delete an address space of a reduced hardware resource from the current address space, and update a system resource view. Through the embodiments of the present invention, the extendibility of a tightly coupled shared memory system can be guaranteed, and the design complexity and cost of the multiway system also can be greatly reduced, which improves the flexibility and reusability of the system.

Abstract: A method for building a multi-processor system with nodes having multiple cache coherency domains. In this system, a directory built in a node controller needs to include processor domain attribute information, and the information can be acquired by configuring cache coherency domain attributes of ports of the node controller connected to processors. In the disclosure herein, the node controller can support the multiple physical cache coherency domains in a node.

Abstract: A design method of a repeater chip is provided, the repeater chip designed by using the method can implement interconnection among nodes, and implement packet sequence receiving, classifying, storing, forwarding, sorting, and transmitting functions of the repeater chip, thereby implementing effective extension of a high-speed transmission link among the nodes, so as to reduce hardware design difficulties and design risks. The structure of the repeater chip is formed by: an interface detecting unit, a sequence storing unit, a sequence forwarding unit, a sequence determining unit, and a sequence sorting unit.

Abstract: A differential signal reversion and correction circuit and a method thereof are provided. The structures of the circuit include: a data frame sending module, when the link conditions are detected, the data frame sending module generates specific logic sequence and finishes the sending by a input/output port, such that a receiving side receives, processes and analyzes the sequence, and determination of link transmission conditions are achieved; a comparator of the receiving side, which receives sequence data, performs corresponding comparing, checking and feedback controlling, thereby achieving link detection and differential correction purpose; a reversion control signal generating module, which receives a comparison result of the comparator, generates corresponding control signal, and controls the link whether to perform reversion operation.

Abstract: A method of implementing packet search by double sliding windows is provided. The method adopts a three-level barrel shift register to store input packet data, and a position of a sliding window 1 is determined at 32 positions by primary testing of a link, so as to ensure that the packet data is located at the center of the sliding window 1, thereby ensuring that the position of the sliding window 1 meets a transmission characteristic of a specific link to the maximum extent. After the position of the sliding window 1 is determined, 32-bit packet data can be effectively searched in the sliding window 1 by dynamically adjusting a sliding window 2, and 32-bit transmission offset is allowed for the packet data. The method of implementing packet search by double sliding windows meets a transmission characteristic of a specific link to the maximum extent.

Abstract: An extension Cache Coherence protocol-based multi-level coherency domain simulation verification and test method. An extension Cache Coherence protocol-based multi-level coherency domain CC-NUMA (Cache Coherent Non-Uniform Memory Access) system protocol simulation model is built, a protocol table inquiring and state converting executing mechanism in a key node of a system ensures that a Cache Coherence protocol is maintained in a single computing domain and is simultaneously maintained among a plurality of computing domains, and accuracy and stability of intra-domain and inter-domain transmission are ensured; a credible protocol inlet conversion coverage rate evaluation driven verification method is provided, transactions are processed by loading an optimized transaction generator push model, a coverage rate index is obtained after the operation is ended, and the verification efficiency is increased in comparison with a random transaction promoting mechanism.

Abstract: A design method of a repeater chip is provided, the repeater chip designed by using the method can implement interconnection among nodes, and implement packet sequence receiving, classifying, storing, forwarding, sorting, and transmitting functions of the repeater chip, thereby implementing effective extension of a high-speed transmission link among the nodes, so as to reduce hardware design difficulties and design risks. The structure of the repeater chip is formed by: an interface detecting unit, a sequence storing unit, a sequence forwarding unit, a sequence determining unit, and a sequence sorting unit.

Abstract: A method for building a multi-processor system with nodes having multiple cache coherency domains. In this system, a directory built in anode controller needs to include processor domain attribute information, and the information can be acquired by configuring cache coherency domain attributes of ports of the node controller connected to processors. In the disclosure herein, the node ca roller can support the multiple physical cache coherency domains in a node.

Abstract: A method of constructing a Share-F state in a local domain of a multi-level cache coherency domain system, includes: 1) when it is requested to access S state remote data at the same address, determining an accessed data copy by inquiring a remote proxy directory RDIR, and determining whether the data copy is in an inter-node S state and an intra-node F state; 2) directly forwarding the data copy to a requester, and recording the data copy of the current requester as an inter-node Cache coherency domain S state and an intra-node Cache coherency domain F state; and 3) after data forwarding is completed, recording, in a remote data directory RDIR, an intra-node processor losing an F permission state as the inter-node Cache coherency domain S state and the intra-node Cache coherency domain F state.

Abstract: A prototype verification system and method are provided for a high-end fault-tolerant computer. The system includes multiple single junction prototype verification systems and an interconnection router chipset. The single junction prototype verification systems are interconnected through the interconnection router chipset. Each single junction prototype verification system includes a computer board which is a four-path tightly-coupled computer board, and a chip verification board including two junction controller chipsets. Each junction controller chipset includes two field-programmable gate array (FGPA) chips which bear a logic of one junction controller together, and an interconnection board including two FGPA chips. Each FPGA chip provides a high speed interconnection port used to achieve protocol interconnection between two paths of the computer board and one of the junction controller chipsets.

Abstract: The present invention provides a high-end fault-tolerant computer system and an implementation method. The system includes N single junction prototype verification systems and M crossbar-switch interconnection router chipsets. Each crossbar-switch interconnection router chipset is used to achieve the interconnection among the N single junction prototype verification systems. Switching is not performed among all crossbar-switch interconnection router chipsets, and both M and N are positive integers greater than or equal to 2. The single junction includes: a computer board, which is 4-path tightly-coupled computer board, and a junction controller for controlling 2 paths of CPUs on the computer board. The present invention can effectively realize the global memories sharing, balance the system transmission bandwidth and delay, and solve the problem of the integration reliability of multi-path CPU system.

Abstract: A prototype verification system and method are provided for a high-end fault-tolerant computer. The system includes multiple single junction prototype verification systems and an interconnection router chipset. The single junction prototype verification systems are interconnected through the interconnection router chipset. Each single junction prototype verification system includes a computer board which is a four-path tightly-coupled computer board, and a chip verification board including two junction controller chipsets. Each junction controller chipset includes two field-programmable gate array (FGPA) chips which bear a logic of one junction controller together, and an interconnection board including two FGPA chips. Each FPGA chip provides a high speed interconnection port used to achieve protocol interconnection between two paths of the computer board and one of the junction controller chipsets.

Abstract: The present invention provides a high-end fault-tolerant computer system and an implementation method. The system includes N single junction prototype verification systems and M crossbar-switch interconnection router chipsets. Each crossbar-switch interconnection router chipset is used to achieve the interconnection among the N single junction prototype verification systems. Switching is not performed among all crossbar-switch interconnection router chipsets, and both M and N are positive integers greater than or equal to 2. The single junction includes: a computer board, which is 4-path tightly-coupled computer board, and a junction controller for controlling 2 paths of CPUs on the computer board. The present invention can effectively realize the global memories sharing, balance the system transmission bandwidth and delay, and solve the problem of the integration reliability of multi-path CPU system.