Abstract: Provided is a sensing apparatus comprising a chip for integrated amplification and sequencing of a template polynucleotide in a sample. The apparatus comprises a chip with at least one ISFET in a well or chamber, amplification means for amplifying the template polynucleotide on a surface of said chip and comprising at least one heating means suitable for conducting amplification of the template polynucleotide at temperatures elevated with respect to room temperature, and sequencing means for sequencing the amplified template polynucleotide in said well or chamber. Methods of use are also provided.

Abstract: Provided is a sensing apparatus comprising a chip for integrated amplification and sequencing of a template polynucleotide in a sample. The apparatus comprises a chip with at least one ISFET in a well or chamber, amplification means for amplifying the template polynucleotide on a surface of said chip and comprising at least one heating means suitable for conducting amplification of the template polynucleotide at temperatures elevated with respect to room temperature, and sequencing means for sequencing the amplified template polynucleotide in said well or chamber. Methods of use are also provided.

Abstract: Provided is a sensing apparatus comprising a chip for integrated amplification and sequencing of a template polynucleotide in a sample. The apparatus comprises a chip with at least one ISFET in a well or chamber, amplification means for amplifying the template polynucleotide on a surface of said chip and comprising at least one heating means suitable for conducting amplification of the template polynucleotide at temperatures elevated with respect to room temperature, and sequencing means for sequencing the amplified template polynucleotide in said well or chamber. Methods of use are also provided.

Abstract: Provided is a sensing apparatus comprising a chip for integrated amplification and sequencing of a template polynucleotide in a sample. The apparatus comprises a chip with at least one ISFET in a well or chamber, amplification means for amplifying the template polynucleotide on a surface of said chip and comprising at least one heating means suitable for conducting amplification of the template polynucleotide at temperatures elevated with respect to room temperature, and sequencing means for sequencing the amplified template polynucleotide in said well or chamber. Methods of use are also provided.

Abstract: Provided is a sensing apparatus comprising a chip for integrated amplification and sequencing of a template polynucleotide in a sample. The apparatus comprises a chip with at least one ISFET in a well or chamber, amplification means for amplifying the template polynucleotide on a surface of said chip and comprising at least one heating means suitable for conducting amplification of the template polynucleotide at temperatures elevated with respect to room temperature, and sequencing means for sequencing the amplified template polynucleotide in said well or chamber. Methods of use are also provided.

Abstract: Provided is a sensing apparatus comprising a chip for integrated amplification and sequencing of a template polynucleotide in a sample. The apparatus comprises a chip with at least one ISFET in a well or chamber, amplification means for amplifying the template polynucleotide on a surface of said chip and comprising at least one heating means suitable for conducting amplification of the template polynucleotide at temperatures elevated with respect to room temperature, and sequencing means for sequencing the amplified template polynucleotide in said well or chamber. Methods of use are also provided.

Abstract: According to a first aspect of the present invention there is provided a digital signal processing circuit, one or more switches of the circuit being provided by an ion sensitive field effect transistor.

Abstract: A signal processing circuit includes an ion sensitive field effect transistor, a reference electrode for the ion sensitive field effect transistor, a metal oxide semiconductor transistor having its gate coupled to the reference electrode, and a biasing circuit. The biasing circuit is configured to bias the ion sensitive field effect transistor and the metal oxide semiconductor field effect transistor to operate in a weak inversion region and to provide an output current signal.

Abstract: A signal processing circuit comprising one or more ion sensitive field effect transistors, ISFETs, and a biasing circuit for biasing the or each ion sensitive field effect transistor to operate in the weak inversion region.