Abstract: Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The symbols of the received signal vectors are combined, forming a combined received signal vector that may be treated as a single received signal vector. The combined signal vector is then decoded using a maximum-likelihood decoder. In some embodiments, the combined received signal vector may be processed prior to decoding. Systems and methods are also provided for computing soft information from a combined signal vector based on a decoding metric. Computationally intensive calculations can be extracted from the critical path and implemented in preprocessors and/or postprocessors.

Abstract: Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The symbols of the received signal vectors are combined, forming a combined received signal vector that may be treated as a single received signal vector. The combined signal vector is then decoded using a maximum-likelihood decoder. In some embodiments, the combined received signal vector may be processed prior to decoding. Systems and methods are also provided for computing soft information from a combined signal vector based on a decoding metric. Computationally intensive calculations can be extracted from the critical path and implemented in preprocessors and/or postprocessors.

Abstract: Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where a receiver has received one or more signal vectors from the same transmitted vector. The receiver processes these received signal vectors one by one, and uses information from signal vectors that have already been processed to process the next signal vector. To process a current signal vector, the receiver concatenates the current signal vector with a previously processed signal vector. This concatenated signal vector is decoded using, for example, a maximum-likelihood (ML). To decode the concatenated signal vector, the ML decoder can use a concatenated channel matrix that includes a channel response matrix associated with the current signal vector and a processed version of previous channel response matrices.

Abstract: In a method for synchronizing a receiver to a synchronous signal, in a signal having been processed based on an automatic gain control (AGC) with a varying gain, a symbol is detected. An estimated beginning of a subsequent frame is determined based on the detected symbol. A gain of the AGC is fixed for a period during which the estimated start of the subsequent frame is processed by the AGC. A transform of the signal is analyzed to determine if the estimated start of the subsequent frame corresponds to an actual start of the subsequent frame. If the estimated start of the subsequent frame does not corresponds to the actual start of the subsequent frame, the gain of the AGC is allowed to resume varying and, a further symbol in the signal is detected, the signal having been processed based on the varying gain of the AGC.

Abstract: In a method for synchronizing a receiver to a synchronous signal, a plurality of potential symbols are detected in a signal, the signal having been processed based on automatic gain control (AGC) with a varying gain. Next frame potential symbols corresponding to potential symbols in the plurality of potential symbols are determined, the next frame potential symbols being in frames subsequent to the frames in which the corresponding potential symbols are located. A gain of the AGC is fixed for each corresponding symbol interval during which a next frame potential symbol is operated on by the AGC. In between next frame potential symbols, the AGC is allowed to vary. Next frame potential symbols are analyzed after a transform is calculated to determine if any correspond to a start of a frame.

Abstract: A method and apparatus are disclosed for power management of an electronic device. The present invention reduces power consumption of an electronic device that communicates over a network by selecting a transmission mode with reduced power consumption as the battery level gets lower. A disclosed power management process monitors the battery level of an electronic device and selects a transmission mode (e.g., a transmission rate) with a lower power consumption when the battery power level reaches one or more predefined threshold levels.

Abstract: A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

Abstract: A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

Abstract: Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where a receiver has received one or more signal vectors from the same transmitted vector. The receiver processes these received signal vectors one by one, and uses information from signal vectors that have already been processed to process the next signal vector. To process a current signal vector, the receiver concatenates the current signal vector with a previously processed signal vector. This concatenated signal vector is decoded using, for example, a maximum-likelihood (ML). To decode the concatenated signal vector, the ML decoder can use a concatenated channel matrix that includes a channel response matrix associated with the current signal vector and a processed version of previous channel response matrices.

Abstract: Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The symbols of the received signal vectors are combined, forming a combined received signal vector that may be treated as a single received signal vector. The combined signal vector is then decoded using a maximum-likelihood decoder. In some embodiments, the combined received signal vector may be processed prior to decoding. Systems and methods are also provided for computing soft information from a combined signal vector based on a decoding metric. Computationally intensive calculations can be extracted from the critical path and implemented in preprocessors and/or postprocessors.

Abstract: Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The symbols of the received signal vectors are combined, forming a combined received signal vector that may be treated as a single received signal vector. The combined signal vector is then decoded using a maximum-likelihood decoder. In some embodiments, the combined received signal vector may be processed prior to decoding. Systems and methods are also provided for computing soft information from a combined signal vector based on a decoding metric. Computationally intensive calculations can be extracted from the critical path and implemented in preprocessors and/or postprocessors.

Abstract: Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The receiver combines the received vectors by vector concatenation The concatenated vector may then be decoded using, for example, maximum-likelihood decoding. In some embodiments, the combined signal vector is equalized before decoding.

Abstract: A method of decoding interleaved Reed-Solomon codes to achieve an improved performance for burst errors is described. The method takes advantage of both interleaving and erasure decoding to increase the error correcting capability of a system without necessarily depending on channel reliability information. The observed correlation of burst errors in interleaved systems is advantageously used to achieve an improved error-correcting system, wherein a first code word is decoded, and the error locations in the first codeword are used to determine erasures for the remaining code words in the same interleaving block, and finally, decoding the remaining code words in parallel.

Abstract: A Reed Solomon decoder architecture. The architecture uses a modified version of the error-evaluator polynomial form proposed by Horiguchi, and later improved by Feng. The architecture is an improvement over Feng in that the area of the dominant PDU unit has been significantly reduced, while maintaining nearly the same iteration time, in novel slice circuitry which rotates terms to share a common multiplier and other circuitry. In addition, a novel implementation of storage of the B polynomial and associated overflow flags allows its storage to be minimized and provides equivalent functioning of the Chien search unit using a proprietary dual-multiplier arrangement in place of random multipliers used by Feng.

Abstract: A Reed Solomon decoder architecture that uses a modified version of the error-evaluator polynomial form having a significantly reduced area of the dominant PDU unit, without loss in iteration time, in slice circuitry, which rotates terms to share a common multiplier and other circuitry. In addition, a B polynomial is stored, and associated overflow flags are implemented, to allow its storage to be minimized using a dual-multiplier arrangement. The decoder for error correcting codes comprises a syndrome calculation circuit, and a polynomial determining unit comprising slices, and a single multiplier in each of the slices, wherein each of the slices is employed a plurality of times in successive clock cycles. A correction circuit comprises a first multiplier employed when a scratch polynomial has overflowed, and a second multiplier employed when not overflowed.

Abstract: A data structure, method and protocol wherein synchronization data indicative of a data frame delineation point is inserted within an inter-packet gap (IPG) proximate a data frame during transmission. Optionally, a cyclical redundancy check (CRC) length indicative data, pointer data, and other data is inserted within the IPG to further insure appropriate delineation of data frames within a data stream.

Abstract: A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

Abstract: A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

Abstract: A method and apparatus are disclosed for power management of an electronic device. The present invention reduces power consumption of an electronic device that communicates over a network by selecting a transmission mode with reduced power consumption as the battery level gets lower. A disclosed power management process monitors the battery level of an electronic device and selects a transmission mode (e.g., a transmission rate) with a lower power consumption when the battery power level reaches one or more predefined threshold levels.

Abstract: A Reed Solomon decoder architecture. The architecture uses a modified version of the error-evaluator polynomial form proposed by Horiguchi, and later improved by Feng. The architecture is an improvement over Feng in that the area of the dominant PDU unit has been significantly reduced, while maintaining nearly the same iteration time, in novel slice circuitry which rotates terms to share a common multiplier and other circuitry. In addition, a novel implementation of storage of the B polynomial and associated overflow flags allows its storage to be minimized and provides equivalent functioning of the Chien search unit using a proprietary dual-multiplier arrangement in place of random multipliers used by Feng.