Patents by Inventor Leith L. Johnson
Leith L. Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8782779Abstract: A system and method for achieving one or more protected regions within a computer system having multiple partitions are disclosed. In at least some embodiments, the system includes an intermediary device for use within the computer system having the multiple partitions. The intermediary device includes a fabric device, and a first firewall device capable of limiting communication of a signal based upon at least one of a source of the signal and an intended destination of the signal, the first firewall device being at least indirectly coupled to the fabric device. The intermediary device further includes a first conversion device that is one of integrated with the first firewall device and distinct from the first firewall device, and that is capable of converting between a processor address and a fabric address for use by the fabric device. In some embodiments, the various devices each include Control and Status Registers (CSRs).Type: GrantFiled: September 26, 2007Date of Patent: July 15, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Chris M. Giles, Russ W. Herrell, John A. Morrison, Andrew R. Wheeler, Gerald J. Kaufman, Jr., Leith L. Johnson, Daniel Zilavy
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Patent number: 8386702Abstract: In one embodiment, a memory control system is provided with a memory controller having 1) a first interface to receive memory read/write requests; 2) a second interface to read/write data from a number of memory modules; 3) a memory cache containing spare memory locations; and 4) logic to, upon receipt of a memory read/write request, i) direct the read/write request to the memory cache when an address associated with the read/write request resides in the memory cache, and ii) direct the read/write request to the second interface when the address associated with the read/write request does not reside in the memory cache.Type: GrantFiled: October 27, 2005Date of Patent: February 26, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Larry J. Thayer, Leith L. Johnson
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Patent number: 7624234Abstract: A directory cache is provided with a plurality of directory entries configured to store information regarding copies of memory lines stored in a plurality of caches. The entries are divided into sets of N entries, with each set of N entries being addressable via an index. The directory cache is also provided with a cache controller. The cache controller retrieves a set of N entries associated with an index corresponding to a memory line, and if a tag portion of one of the retrieved entries corresponds to the memory line, the cache controller determines whether the one of the retrieved entries contains an indication that information regarding the memory line is stored in at least a second one of the retrieved entries.Type: GrantFiled: August 31, 2006Date of Patent: November 24, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Erin A. Handgen, Leith L. Johnson
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Publication number: 20090083505Abstract: A system and method for achieving one or more protected regions within a computer system having multiple partitions are disclosed. In at least some embodiments, the system includes an intermediary device for use within the computer system having the multiple partitions. The intermediary device includes a fabric device, and a first firewall device capable of limiting communication of a signal based upon at least one of a source of the signal and an intended destination of the signal, the first firewall device being at least indirectly coupled to the fabric device. The intermediary device further includes a first conversion device that is one of integrated with the first firewall device and distinct from the first firewall device, and that is capable of converting between a processor address and a fabric address for use by the fabric device. In some embodiments, the various devices each include Control and Status Registers (CSRs).Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Inventors: Chris M. Giles, Russ W. Herrell, John A. Morrison, Andrew R. Wheeler, Gerald J. Kaufman, JR., Leith L. Johnson, Daniel Zilavy
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Patent number: 7451249Abstract: Method and apparatus for allowing a direct memory access unit to have access to a virtual address space is accomplished by receiving a request for memory access from the direct memory access device; determining a device identifier according to the received request for memory access; determining a memory protection schema according to the determined device identifier; and granting the direct memory access unit access to memory in accordance with the determined memory protection schema.Type: GrantFiled: March 16, 2006Date of Patent: November 11, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Joe P. Cowan, Matthew B. Lovell, Leith L. Johnson, Jonathan K. Ross
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Publication number: 20080059710Abstract: A directory cache is provided with a plurality of directory entries configured to store information regarding copies of memory lines stored in a plurality of caches. The entries are divided into sets of N entries, with each set of N entries being addressable via an index. The directory cache is also provided with a cache controller. The cache controller retrieves a set of N entries associated with an index corresponding to a memory line, and if a tag portion of one of the retrieved entries corresponds to the memory line, the cache controller determines whether the one of the retrieved entries contains an indication that information regarding the memory line is stored in at least a second one of the retrieved entries.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Inventors: Erin A. Handgen, Leith L. Johnson
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Patent number: 7103793Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means for receiving data and strobe signals via said pads at Mx double data rate memory speed (M2).Type: GrantFiled: October 14, 2003Date of Patent: September 5, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Eric M. Rentschler, Jeffrey G. Hargis, George T. Letey, Leith L. Johnson
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Patent number: 7103790Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1× double data rate memory speed, and means for receiving data and strobe signals via said pads at M× double data rate memory speed (M?2).Type: GrantFiled: October 28, 2003Date of Patent: September 5, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Eric M. Rentschler, Jeffrey G. Hargis, Leith L. Johnson
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Patent number: 6889335Abstract: Methods and apparatus are disclosed herein for providing tri-state noise immunity for memory systems such as DDR memory systems, wherein 1) there are large variations in read data loop delay, and 2) strobe buses have similar termination and threshold voltages. In one embodiment, strobe receiver circuitry includes a counter and counter control logic. The counter updates a count in response to strobe edges of received strobe signals. The counter control logic enables the counter before each strobe signal is received by generating control signals asynchronously with respect to the received strobe signals. The counter control logic also resets the counter after each strobe signal is received by receiving feedback from the counter and, in response to the feedback, resetting the counter asynchronously with respect to the received strobe signals. The strobe receiver circuitry may form part of a DDR memory controller.Type: GrantFiled: April 7, 2001Date of Patent: May 3, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jeffrey G. Hargis, Eric M. Rentschler, Leith L. Johnson
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Publication number: 20040133757Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means for receiving data and strobe signals via said pads at Mx double data rate memory speed (M2).Type: ApplicationFiled: October 14, 2003Publication date: July 8, 2004Inventors: Eric M. Rentschler, Jeffrey G. Hargis, George T. Letey, Leith L. Johnson
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Publication number: 20040088512Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1× double data rate memory speed, and means for receiving data and strobe signals via said pads at M× double data rate memory speed (M≧2).Type: ApplicationFiled: October 28, 2003Publication date: May 6, 2004Inventors: Eric M. Rentschler, Jeffrey G. Hargis, Leith L. Johnson
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Patent number: 6715014Abstract: A module array includes a lead-in transmission line from a driving source. The lead-in transmission line ends with a series impedance between the lead-in transmission line and a star node. The star node has a terminating impedance between it and a termination voltage. At least two branch transmission lines diverge from the star node. Modules connect to the branch transmission lines in a comb topology.Type: GrantFiled: May 25, 2000Date of Patent: March 30, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Leith L Johnson, Michael H. Cogdill
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Patent number: 6678811Abstract: Methods and apparatus for writing data to memory are disclosed herein. In general, the methods and apparatus provide a memory controller with means for writing data at different rates. Data may need to be written to memory at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, comprise demultiplexers which receive data from the memory controller at twice the rate which data could be written directly to a memory module. The intermediary chip may then simultaneously transmit the demultiplexed write data to memory modules in two or more banks of memory modules.Type: GrantFiled: April 7, 2001Date of Patent: January 13, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Eric M. Rentschler, Jeffrey G. Hargis, Leith L. Johnson
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Patent number: 6633965Abstract: Methods and apparatus for receiving data from memory, the data being associated with a strobe, are disclosed herein. In general, the methods and apparatus provide a memory controller with a means for receiving data at different rates. Data may be received by a memory controller at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, include multiplexers which receive data from two or more banks of memory modules and then multiplex the data into one or more data streams which are then transmitted to the memory controller at twice the rate which the memory modules in either bank could transmit data to the memory controller.Type: GrantFiled: April 7, 2001Date of Patent: October 14, 2003Inventors: Eric M. Rentschler, Jeffrey G. Hargis, Leith L. Johnson
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Publication number: 20020172079Abstract: Methods and apparatus are disclosed herein for providing tri-state noise immunity for memory systems such as DDR memory systems, wherein 1) there are large variations in read data loop delay, and 2) strobe buses have similar termination and threshold voltages. In one embodiment, strobe receiver circuitry includes a counter and counter control logic. The counter updates a count in response to strobe edges of received strobe signals. The counter control logic enables the counter before each strobe signal is received by generating control signals asynchronously with respect to the received strobe signals. The counter control logic also resets the counter after each strobe signal is received by receiving feedback from the counter and, in response to the feedback, resetting the counter asynchronously with respect to the received strobe signals. The strobe receiver circuitry may form part of a DDR memory controller.Type: ApplicationFiled: April 7, 2001Publication date: November 21, 2002Inventors: Jeffrey G. Hargis, Eric M. Rentschler, Leith L. Johnson
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Publication number: 20020147896Abstract: Methods and apparatus for writing data to memory are disclosed herein. In general, the methods and apparatus provide a memory controller with means for writing data at different rates. Data may need to be written to memory at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, comprise demultiplexers which receive data from the memory controller at twice the rate which data could be written directly to a memory module. The intermediary chip may then simultaneously transmit the demultiplexed write data to memory modules in two or more banks of memory modules.Type: ApplicationFiled: April 7, 2001Publication date: October 10, 2002Inventors: Eric M. Rentschler, Jeffrey G. Hargis, Leith L. Johnson
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Publication number: 20020147892Abstract: Methods and apparatus for receiving data from memory, the data being associated with a strobe, are disclosed herein. In general, the methods and apparatus provide a memory controller with a means for receiving data at different rates. Data may be received by a memory controller at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, include multiplexers which receive data from two or more banks of memory modules and then multiplex the data into one or more data streams which are then transmitted to the memory controller at twice the rate which the memory modules in either bank could transmit data to the memory controller.Type: ApplicationFiled: April 7, 2001Publication date: October 10, 2002Inventors: Eric M. Rentschler, Jeffrey G. Hargis, Leith L. Johnson
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Patent number: 5987576Abstract: A memory controller and at least one memory module exchange data at high transfer rates by minimizing clock skew. When writing data to the memory module, the memory controller generates a clock signal that travels along a first clock line segment. The data bus carries the write data, and the electrical characteristics of the data bus and first clock line segment are matched such that incident wavefronts of the data bus and clock signal arrive at the memory module in fixed relation to one another. When reading data, the first clock line segment is looped back from the memory module to the memory controller along a second clock line segment, with a copy of the clock signal provided on the second clock line segment. The data bus carries the read data, and the electrical characteristics of the data bus and the first clock line segment are matched such that incident wavefronts of the data bus and clock signal arrive at the memory controller in fixed relationship to one another.Type: GrantFiled: February 27, 1997Date of Patent: November 16, 1999Assignee: Hewlett-Packard CompanyInventors: Leith L. Johnson, David A. Fotland
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Patent number: 5928346Abstract: A PC bus architecture that is compatible with an industry standard bus architecture and allows devices to transfer data more effeciently. The protocol of the present invention allows a data transaction in which a data transfer request can be made by a bus master device and then queued so that the transaction occurs at a later time allowing the bus to be free for other transactions until the responding device has prepared the data.Type: GrantFiled: June 11, 1997Date of Patent: July 27, 1999Assignee: Hewlett-Packard CompanyInventors: Leith L. Johnson, Richard Carlson
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Patent number: 5870573Abstract: A plurality of MOSFET switches, one per bus line, are used to solve the problem of interfacing between two incompatible devices via a single shared bus. The MOSFET switches used are simple, inexpensive, and very fast. The switches perform two primary functions: 1) isolation of two bus sections (possibly for loading reasons); and 2) translation of incompatible voltages transmitted over the bus.Type: GrantFiled: October 18, 1996Date of Patent: February 9, 1999Assignee: Hewlett-Packard CompanyInventor: Leith L. Johnson