Abstract: A display drive circuit, a drive method thereof, and a display device are disclosed. The display drive circuit includes: a pixel circuit and a compensation circuit, the pixel circuit includes: a drive transistor, a light emitting device, a storage capacitor, and a gating sub-circuit configured to control connection and disconnection between the control electrode of the drive transistor and a control terminal of the compensation circuit and connection and disconnection between a second electrode of the light emitting device and a sensing terminal of the compensation circuit in response to a signal of a scanning line; the compensation circuit includes: a voltage generating sub-circuit configured to generate a sensing voltage according to the drive current and a target data voltage, and a voltage adjusting sub-circuit configured to adjust a voltage of the control terminal according to the sensing voltage and a voltage of a second power supply terminal.

Abstract: A display drive circuit, a drive method thereof, and a display device are disclosed. The display drive circuit includes: a pixel circuit and a compensation circuit, the pixel circuit includes: a drive transistor, a light emitting device, a storage capacitor, and includes: a gating sub-circuit configured to control connection and disconnection between the control electrode of the drive transistor and a control terminal of the compensation circuit and connection and disconnection between a second electrode of the light emitting device and a sensing terminal of the compensation circuit in response to a signal of a scanning line; the compensation circuit includes: a voltage generating sub-circuit configured to generate a sensing voltage according to the drive current and a target data voltage, and a voltage adjusting sub-circuit configured to adjust a voltage of the control terminal according to the sensing voltage and a voltage of a second power supply terminal.

Abstract: A display driving system includes a timing controller, a level shifter and a power supply circuit. The timing controller is configured to send first clock signals having a first level, a second level and a third level to the level shifter. The second level is less than the first level and greater than the third level. The power supply circuit is configured to output a first, second and third voltage signals to the level shifter. The second voltage signal has a second voltage less than a first voltage of the first voltage signal and greater than a third voltage of the third voltage signal. The level shifter is configured to transmit the first voltage in response to the first level, the second voltage to in response to the second level and the third voltage in response to the third level, to a gate driver circuit.

Abstract: An array substrate, a display panel, a display device, an operating method, and a manufacturing method are disclosed. The array substrate includes a wiring structure formed on a base substrate, and the wiring structure includes a common electrode line for connecting a common electrode, and a plurality of signal lines. The plurality of signal lines include at least one pair of signal lines, and the pair of signal lines include a first signal line and a second signal line. The first signal line is disposed on a first side of the common electrode line and is configured to transmit a driving signal for a gate driving circuit. The second signal line is disposed on a second side of the common electrode line and is configured to transmit an inverted signal of the driving signal.

Abstract: An array substrate, a display panel, a display device, an operating method, and a manufacturing method are disclosed. The array substrate includes a wiring structure formed on a base substrate, and the wiring structure includes a common electrode line for connecting a common electrode, and a plurality of signal lines. The plurality of signal lines include at least one pair of signal lines, and the pair of signal lines include a first signal line and a second signal line. The first signal line is disposed on a first side of the common electrode line and is configured to transmit a driving signal for a gate driving circuit. The second signal line is disposed on a second side of the common electrode line and is configured to transmit an inverted signal of the driving signal.