Patents by Inventor Lekshmi C

Lekshmi C has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and apparatus to generate circuit timing constraint predictions using machine learning
    Patent number: 12699829
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for methods and apparatus to generate I/O timing constraint predictions for system-on-chips using machine learning. An apparatus is disclosed herein comprising at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to extract delay features from a first system-on-chip design and a second system-on-chip design, apply a machine learning model to the extracted delay features to determine an estimated delay for the first system-on-chip design, compare the estimated delay for the first system-on-chip design to the second system-on-chip design to determine an error of the first system-on-chip design, and update the second system-on-chip design based on the error determined for the first system-on-chip design.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: August 4, 2026
    Assignee: Intel Corporation
    Inventors: Lekshmi C, Sourav Saha, Anmol Khatri, Raj Chetan Yadav, Rakshit Bazaz, Shivangi Gupta
  • METHODS AND APPARATUS TO GENERATE CIRCUIT TIMING CONSTRAINT PREDICTIONS USING MACHINE LEARNING
    Publication number: 20240078368
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for methods and apparatus to generate I/O timing constraint predictions for system-on-chips using machine learning. An apparatus is disclosed herein comprising at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to extract delay features from a first system-on-chip design and a second system-on-chip design, apply a machine learning model to the extracted delay features to determine an estimated delay for the first system-on-chip design, compare the estimated delay for the first system-on-chip design to the second system-on-chip design to determine an error of the first system-on-chip design, and update the second system-on-chip design based on the error determined for the first system-on-chip design.
    Type: Application
    Filed: November 9, 2022
    Publication date: March 7, 2024
    Inventors: Lekshmi C, Sourav Saha, Anmol Khatri, Raj Chetan Yadav, Rakshit Bazaz, Shivangi Gupta