Abstract: A mini-cache module is added to a computer system to increase throughput or may also be added to enhance the functionality of a general cache memory unit. The mini-cache module refills and stores frequently used data words concurrently during processor operations and provides them to the processor, eliminating the need to access a system bus to main memory. A data queue storage stores a data block of words from main memory and makes them available to requests from the main processor (if the requested address matches an address register block in the mini-cache). If an address "hit" occurs, then the mini-cache will prevent any system bus request to main memory and additionally will monitor the system bus for any "Write" operations which might feasibly change the validity of data in the data storage block of the mini-cache. In this case the data stored in the mini-cache is invalidated and cannot be used by the processor.

Abstract: A message transfer system between multiple processors in a network. Each processor includes an interprocessor communications (IPC) hardware unit having an unique address count. An address count generator in a designated IPC hardware unit generates a sequence of binary count numbers such that when the generated count number matches the address of the IPC hardware unit, then that particular hardware unit and its associated processor are granted a time period of bus access for sending messages on the IPC network bus to other processors. Messages on the IPC network bus can be received by an IPC hardware unit at any time irrespective of the generated count number. Any sending processor that has bus access can concurrently provide multiple messages where each of the multiple messages is directed to each particular processor for reception. Thus one sender, with bus access, can communicate with multiple receivers during its transmission onto the IPC network bus connecting the processors.

Abstract: In a digital data transfer system whereby a plurality of driver units are all connected to and share the same common system bus, there is provided control gating logic which will prevent the enablement of a subsequent driver for a fixed delay time until it is certain that the previous driver has been shut down. Due to switching time variations in driving units, a fixed delay time is set to function in a first driver that is beginning its data transmission to be sure that another driver which was previously transmitting data has been completely turned-off before the first driver gains access to the commonly shared bus. This ensures that no two drivers can simultaneously be driving data onto the system bus at the same time which would obviate the integrity of data transmitted.

Abstract: An automatic re-configurable computer system having a standard processor module and standard main memory and I/O control modules where each module is inter-connected to a common system bus. Automatic re-configuration occurs in the standard modules, when an optional module is connected onto the system bus, permitting inter-cooperation between the standard and optional modules to take place.

Abstract: Arbitration and control circuitry for monitoring the two processors sharing a system bus to insure fair access to system resources and to sense error conditions which occur in order to hold access for the processor involved until the error condition is cleared. The arbitration circuitry provides for two levels of bus access requests where one level involves normal requests and a second level involves priority request which take precedence over normal requests.

Abstract: A programmable array logic unit (PAL) having a disconnected array of gates, inverters and D-Type flip-flops, is utilized by burning-in the interconnections, to enable the D flip-flops to function as J-K flip-flops and/or toggle flip-flops to enable flexibility in the functions available for utilization, by providing inputs for Direct Set, Direct Clear and Hold.

Abstract: A system wherein multiple sources of data each have drivers for transmitting data to a common system bus. The drivers are each managed by individual enabling logic which is controlled by a flip-flop driven by a clock. Thus no driver can connect and drive data onto the bus until one clock period after the previously connected driver has been disabled and disconnected from the bus.